Features; Register Protection - STMicroelectronics SPC572L series Reference Manual

RM0400
13.1.2

Features

The SIUL2 supports these distinctive features:
•
7 GPIO ports with data control
–
–
•
Two 16-bit registers can be read/written with one access to a 32-bit port if needed.
•
External interrupt/DMA request support with:
–
–
–
–
Additionally the SIUL2 contains the multiplexed signal configuration registers that configure
the electrical parameters and settings of all 85 functional pads. These are used to configure
the following pad features:
• Drive strength
•
Output impedance control
• Open drain/source output enable
•
Slew rate control of JTAG pins
• Internal weak pull control
•
Pin function assignment
•
Control of analog path switches
•
Safe mode behavior configuration
•
TTL or CMOS or Automotive input levels
13.1.3

Register protection

The System Integration Unit Lite2 uses the Register Protection Scheme to protect the
individual registers from accidental writes. The following registers can be protected:
•
SIUL2 DMA/Interrupt Request Enable Register 0 (SIUL2_DIRER0)
•
SIUL2 DMA/Interrupt Request Select Register 0 (SIUL2_DIRSR0)
•
SIUL2 Interrupt Rising-Edge Event Enable Register 0 (SIUL2_IREER0)
•
SIUL2 Interrupt Falling-Edge Event Enable Register 0 (SIUL2_IFEER0)
•
SIUL2 Interrupt Filter Enable Register 0 (SIUL2_IFER0)
•
SIUL2 Interrupt Filter Maximum Counter Register (SIUL2_IFMCR0–SIUL2_IFMCR31)
•
SIUL2 Interrupt Filter Clock Prescaler Register (SIUL2_IFCPR)
•
SIUL2 I/O pin Multiplexed Signal Configuration Registers (SIUL2_MSCR_IO_0–
SIUL2_MSCR_IO_511)
•
SIUL2 Multiplexed Signal Configuration Registers for Multiplexed Input Selection
(SIUL2_MSCR_MUX_512–SIUL2_MSCR_MUX_1023)
Details regarding the protected registers at specific addresses can be found in
Section 6.7.12: Register protection (REG_PROT) configuration
Protection
Drive data to up to 16 independent I/O channels
Sample data from up to 16 independent I/O channels
2 system interrupt vectors for 3 interrupt sources connected to EIRQ pins with
independent interrupt mask
3 programmable digital glitch filters (one for each EIRQ pin)
Independent DMA channel for each EIRQ pin
Edge detection
(REG_PROT).
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System Integration Unit Lite2 (SIUL2)
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