Modes Of Operation - STMicroelectronics SPC572L series Reference Manual

RM0400
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Generation of 103 interrupt requests and or DMA requests.
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Debugger is allowed to read all GTM registers through the peripheral bus even when
the timer is running. Read-access of the debugger is possible without destroying or
changing the contents of these registers.
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Debugger is allowed to read all GTM addresses read-/writeable from the peripheral bus
when GTM is running or halted.
43.1.2

Modes of operation

43.1.2.1 Normal Mode
The normal mode is the mode in which the GTMINT module is after a reset is applied. In this
mode the timer IP is functional and processes input timing signals and generates timed
outputs based on the input timing signals or controlled by the internal channels software.
The GTMDI development interface is also active.
43.1.2.2 Stop Mode
This mode is set when the global stop input is received or when field GTMMCR[MDIS] is
asserted. In this case all functional clocks are disabled (ipg_clk and ipg_clk_gtm), but the
slave bus clock is not disabled. Please see more details on
Description.
43.1.2.3 Debug Mode (or Halt Mode)
The debug mode or GTM-IP halt mode is externally requested through the GTMDI. In this
mode, the GTM-IP main clock is requested to stop (ipg_clk_gtm only) and the bus interface
clocks remain running to access all registers and memories. It is possible to read the
registers not interfering into the logic status, even for FIFOs, by configuring the debug
access controls on GTMDI.
43.1.3 Block diagram
Figure 466
– Correctable error indication (correctable data error)
shows the interconnections in the GTMINT module.
DocID027809 Rev 4
GTM101 Integration (GTMINT) Module
Section 43.3.4, Stop Mode
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