STMicroelectronics SPC572L series Reference Manual page 983

RM0400
Offset
MCS Set trigger control register
0x3002C + FFi
(MCS[i]_STRG)
(0x30028 –
0x3002C) + n*0x80
+ FFi
(0x30030 –
0x3003C) + n*0x80
+ FFi
0x30040+n*0x80 + MCS Channel n Program counter register
FFi (MCS[i]_CH[n]_PC)
0x30044+x*0x80 + MCS Channel n interrupt notification register
FFi (MCS[i]_CH[n]_IRQ_NOTIFY)
0x30048+n*0x80 + MCS Channel n interrupt enable register
FFi (MCS[i]_CH[n]_IRQ_EN)
0x3004C+n*0x80 + MCS Channel n software interrupt generation
FFi register (MCS[i]_CH[n]_IRQ_FORCINT)
0x30050+n*0x80 + IRQ mode configuration register
FFi (MCS[i]_CH[n]_IRQ_MODE)
0x30054+n*0x80 + MCS Channel n error interrupt enable
FFi register (MCS[i]_CH[n]_EIRQ_EN)
(0x30058 –
0x30070) + n*0x80 +
FFi
0x30074 + FFi MCS Control register (MCS[i]_CTRL)
0x30078 + FFi MCS Channel reset register (MCS[i]_RST)
0x3007C + FFi
(0x30074 –
0x3007C) + n*0x80
+ FFi
(0x30400 –
0x30FFC) + FFi
0x32000 – 0x37FFC
(0x38000 –
MCS Memory (MCS[i]_MEM)
0x3BFFC) + GGi
(0x3C000 –
0x3FFFC) + GGi
0x48000 – 0x6BFFC
0x6C000 – 0xFFFFC
1. Default value when in reset state.
Table 516. GTMINT module memory map(Continued)
Use
MCS Error register (MCS[i]_ERR)
(GGi = i*0x8000, i = 0..1)
Reserved for MCS2 / 3 / 4 / 5 / 6 Memories
DocID027809 Rev 4
GTM101 Integration (GTMINT) Module
Access
Reserved (n > 0)
Reserved
Reserved
Reserved (n > 0)
Reserved
Reserved for MCS2 / 3 / 4 / 5 / 6 registers
MCS Memories
Reserved
Reserved
(1)
Reset value
R/W 0x0000_0000
0x0000_0000 +
R/W
4*n
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x000X_0000
R/W 0x0000_0000
R/W 0x0000_0000
Location
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
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