Register Descriptions - STMicroelectronics SPC572L series Reference Manual

SENT Receiver (SRX)
Offset
0x0068 + 0x10 CHn_CONFIG—Channel 'n' Configuration Register
× n (n = 0 to (CH-1))
0x006C + 0x10
Reserved
× n
0x0160 + 0x18 CHn_FMSG_DATA—Channel 'n' Fast Message
× n
Register (n = 0 to (CH-1))
0x0164 + 0x18 CHn_FMSG_CRC—Channel 'n' Fast Message
× n
CRC Register (n = 0 to (CH-1))
0x0168 + 0x18 CHn_FMSG_TS—Channel 'n' Fast Message Time
× n
Stamp Register (n = 0 to (CH-1))
0x016C + 0x18 CHn_SMSG_BIT3—Channel 'n' Serial Message
× n Register (Bit 3) (n = 0 to (CH-1))
0x0170 + 0x18 CHn_SMSG_BIT2—Channel 'n' Serial Message
× n
Register (Bit 2) (n = 0 to (CH-1))
0x0174 + 0x18 CHn_SMSG_TS—Channel 'n' Serial Message Time
× n
Stamp Register (n = 0 to (CH-1))
0x02E0 Reserved
1. This bit is either "write 1 to clear" (w1c) or self-clearing depending on the value of the FAST_CLR bit in the
Global Control Register (GBL_CTRL)
49.3.2

Register descriptions

This section describes in address order all the SENT registers and their individual bits.
49.3.2.1 Global Control Register (GBL_CTRL)
This register provides the global control and setting for the SENT Receiver Module. The
SENT_EN bit must be programmed after all other modules settings and control bits have
been written to.
1366/2058
Table 789. SENT memory map(Continued)
Register Name
DocID027809 Rev 4
Access Reset
RW 0x0000_0104
R 0x0000_0000
R 0x0000_0000
R 0x0000_0000
R 0x0000_0000
R 0x0000_0000
R 0x0000_0000
RM0400
Location
49.3.2.20/1392
49.3.2.21/1395
49.3.2.22/1396
49.3.2.23/1396
49.3.2.24/1396
49.3.2.25/1396
49.3.2.26/1396
Section 49.3.2.1: