Table 376. Icimr0–Icimr2 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface
Offset 0x024–0x02C
0 1
R
W
Reset 0 0
16 17
R
W
Reset 0 0
Figure 334. Internal Channel Interrupt Mask Registers (ICIMR0–ICIMR2)
Field
0–31
IM_CH[x]
Parameter num_intch vector has positional inference for registers ICIMR0–2, such that:
• num_intch(i) (i = 0–31) corresponds to ICIMR0 bit[0:31].
•
num_intch(i) (i = 32–63) corresponds to ICIMR1 bit[0:31].
• num_intch(i) (i = 64–95) corresponds to ICIMR2 bit[0:31].
If any of the num_intch(i) value is '0' corresponding bit is not implemented and read access
would return '0' on that bit location. Thus:
•
If num_intch[31:0] is all 0's, register ICIMR0 is not implemented.
• If num_intch[63:32] is all 0's, register ICIMR1 is not implemented.
•
If num_intch[95:64] is all 0's, register ICIMR2 is not implemented.
In any or all of the above circumstances, the corresponding registers are treated as
reserved space and any attempt to access this space generates a transfer error.
36.5.1.7 Watchdog Threshold Interrupt Status Register (WTISR)
This register gives the interrupt status information for the 16 possible upper and 16 possible
lower threshold limits monitored by up to 16 watchdog monitors which can be selected for
each channel.
776/2058
2 3 4 5
0 0 0 0
18 19 20 21
0 0 0 0
Table 376. ICIMR0–ICIMR2 field descriptions
IM_CH[x]: Interrupt mask bit for channel x
0 Interrupt for CH[x] is disabled.
1 Interrupt for CH[x] is enabled.
Table 377. Interrupt Mask Registers to Channel Association
Register
ICIMR0
ICIMR1
ICIMR2
DocID027809 Rev 4
6 7 8 9
IM_CH[x]
0 0 0 0
22 23 24 25
IM_CH[x]
0 0 0 0
Description
Access: User Read/Write
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
Register bits 31:0
IM_CH[31:0]
IM_CH[63:32]
IM_CH[95:64]
14 15
0 0
30 31
0 0