Introduction - STMicroelectronics SPC572L series Reference Manual

RM0400
43 GTM101 Integration (GTMINT) Module
43.1

Introduction

This chapter specifies the functionality of the GTMINT module. The GTMINT is integrated
IP with timer and debug functions and is composed of:
•
The Bosch GTM-IP_101 timer module (also called GTM-IP)
•
The GTMDI debug interface IP
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8 ECC error correction encoder / decoders for the RAMs required by the timer.
The timer GTM-IP_101 is a very complex block that can be configured to perform several
timer functions. The debugger module is the GTMDI IP (GTM Development Interface IP)
that is a Nexus based interface which is connected to the chip level NAR and used to
monitor the software and hardware activities of GTM-IP. The ECC sub-blocks generate the
parity bits on RAM writes and detect errors in the data read from the RAMs.
Note: This chapter does not intend to present details of GTM-IP nor GTMDI. For full information
about the timer and the debugger, please refer to its respective documentation.
43.1.1 Features
The GTMINT module features
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GTM-IP timer features
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GTMDI debug block features
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l. Configuration of GTM has to be confirmed for final silicon
(l)
Time base generators
Advanced data signal / time base router
Input signal processors (16 inputs)
Simple output signal generators (32 outputs)
Microprocessed output signal generators (24 outputs)
Digital PLL
BLDC support
Safety features – GTM is a non-safety relevant module
– Output compare unit
– Monitoring unit
CPU bus interface clock operates asynchronously to timer section clock allowing
CPU low power operation.
Full duplex pin interface for medium and high visibility throughput
– Pin interface shared among all Nexus-based development interfaces on the
device
– Auxiliary Output Port
DATA with MDO (Message Data Out) and MSEO (Message Start/End)
2 EVTO (Event Out) pins for GTM real time signal monitoring
– Auxiliary Input Port
1 EVTI (Event In) pin
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