Clocking - STMicroelectronics SPC572L series Reference Manual

RM0400
21

Clocking

21.1 Introduction
This chapter describes the architecture for the system level clocks and includes the
following information:
•
System clock specifics
•
Clock architecture
•
Clock sources
• Clock monitoring
•
Programmable clock dividers
• Clock control registers
•
Progressive clock switching (PCS)
Note: This chapter covers only clocks that are generated on the device. Protocol clocks that are
provided by external devices are covered in the respective chapters where they are used.
This device boots from the internal 16 MHz RC oscillator (IRCOSC), and uses this as a
backup clock in the event of a PLL or oscillator failure (if backup clock is enabled). The
backup clock can be enabled in the Mode Entry Module (MC_ME). See the "Mode Entry
Module (MC_ME)" chapter for details.
The alternative ways to provide the source clock are:
•
External oscillator/External crystal
•
Internal 16 MHz RC oscillator
From one of these input sources, the internal clocks are generated from PLL0, using
PLL0_PHI and PLL0_PHI1 outputs respectively. These two clocks, along with the XOSC
and IRCOSC, can be selected to drive system peripherals depending on the configuration of
the Auxiliary Clock Selectors in the Clock Generation Module (MC_CGM). Eight Auxiliary
Clock Selectors are available so developers can select an independent clock source for
each system peripheral. There is one additional clock selector that is used exclusively for
the system clock.
Each of the outputs of the module clock selectors have individual dividers that allow for
more clock frequency granularity with the ability to divide the clock selector outputs by up to
512 for a given peripheral. The Clock Monitor Unit (CMU) is connected to IRCOSC, XOSC
and PLL0_PHI as shown in <Cross Refs>Figure 161 (Clock generation) to verify that their
clock frequencies stay within necessary operating limits. The action taken when the CMU
detects an issue with the monitored clock depends on the CMU configuration. When an
issue with a clock is found, the CMU can signal an interrupt or initiate a system reset.
21.2 Clock generation
The top-level clock generation architecture can be seen in
Generation Module (MC_CGM) chapter for details on the Fractional Clock Dividers. All clock
selectors and dividers are located and programmed in the MC_CGM. All dividers are integer
dividers (1, 2, 3, ..., n) with the ranges shown in the divider blocks in
connected to the System Clock Selector must have 50% duty cycle outputs.
Note: The user can select either IRCOSC or XOSC as the reference clock for CMU_0.
DocID027809 Rev 4
Figure 161. See the Clock
Figure 161. All dividers
Clocking
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