Table 956. Once Status Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Table 956
Bit Name
MCLK
m_clk Status Bit
0 MCLK
0 Inactive state
1 Active state
This status bit reflects the logic level on the jd_mclk_on input signal after capture by j_tclk.
ERROR
This bit is used to indicate that an error condition occurred during attempted execution of the
last single-stepped instruction (GO+NoExit with CPUSCR or No Register Selected in
OCMD), and that the instruction may not have been properly executed. This could occur if
1 ERR
an Interrupt (all classes including External, Critical, machine check, Storage, Alignment,
Program, etc.) occurred while attempting to perform the instruction single step. In this case,
the CPUSCR will contain information related to the first instruction of the Interrupt handler,
and no portion of the handler will have been executed.
2 — Reserved, set to zero
RESET Mode
3 RESET
This bit reflects the inverted logic level on the CPU p_reset_b input after capture by j_tclk.
HALT Mode
4 HALT
This bit reflects the logic level on the CPU p_halted output after capture by j_tclk.
STOP Mode
5 STOP
This bit reflects the logic level on the CPU p_stopped output after capture by j_tclk.
Debug Mode
6 DEBUG
This bit is asserted once the CPU is in debug mode. It is negated once the CPU exits debug
mode (even during a debug session)
Waiting Mode
7 WAIT
This bit reflects the logic level on the CPU p_waiting output after capture by j_tclk.
8 0 Reserved, set to 0 for 1149.1 compliance
9 1 Reserved, set to 1 for 1149.1 compliance
57.5.6.2 OnCE Command (OCMD) register
The OnCE Command (OCMD) register is a 10-bit shift register that receives its serial data
from the TDI pin and serves as the instruction register (IR). It holds the 10-bit commands to
be used as input for the OnCE Decoder. The Command Register is shown in
The OCMD is updated when the TAP controller enters the Update-IR state. It contains fields
for controlling access to a resource, as well as controlling single-step operation and exit
from OnCE mode.
Although the OCMD is updated during the Update-IR TAP controller state, the
corresponding resource is accessed in the DR scan sequence of the TAP controller, and as
such, the Update-DR state must be transitioned through in order for an access to occur. In
addition, the Update-DR state must also be transitioned through in order for the single-step
and/or exit functionality to be performed, even though the command appears to have no
data resource requirement associated with it.
provides bit definitions for the OnCE Status register.

Table 956. OnCE Status register field descriptions

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Description
Figure 1009.
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