Figure 688. Transmit Clocks Muxing - STMicroelectronics SPC572L series Reference Manual

LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communications
47.10.4.2 Transmit clock muxing
lfast_pll_ph_clk[0]
Slow Speed
phase 0
47.10.4.3 Tx Request Clock Control
The Tx phase 0 clock is enabled when all the resets are negated.
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Figure 688. Transmit Clocks Muxing

Transmit Side
Glitchless
Mux
Test
Mux
DocID027809 Rev 4
dig_com_if_dl_ph0_clk
Clock
Gating
Cell
Tx
LVDS