Table 809. Chn_Config Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Address Offset = 0x0068 + n × 0x10
0
R
W
Reset 0
8
R
FCRC_CHK IE_PP_DIA
_OFF
W
Reset 0
16
R DCHNG_IN
T
W
Reset 0
24
R
W
Reset 0
Figure 797. Channel 'n' Configuration Register (CHn_CONFIG)
Field
Bus Idle Count: This register value defines the maximum allowable idle period on the sensor
interface of this channel. The value is defined as follows:
0:3
0000: Disabled.
0001: 127*2 Receiver Clock Tick Counts
BUS_IDEL_
CNT 0010: 127*4 Receiver Clock Tick Counts
0100: 127*8 Receiver Clock Tick Counts
1000: 127*16 Receiver Clock Tick Counts
Successive Calibration Check Resynchronized Interrupt Enable: This bit enables interrupt assertion
when Successive Calibration diagnosis has failed three times in case of "Option 2" being selected
for Successive Calibration Check Method and the check resynchronizes the take the third message
4
to be correct.
IE_CAL_RE
SYNC
0 – Interrupt is disabled
1 – Interrupt is enabled
Calibration Variation 20 - 25% Interrupt Enable. This bit enables interrupt assertion when
corresponding status bit is set.
5
IE_CAL_20_
25 0 – Interrupt is disabled
1 – Interrupt is enabled
1 2
BUS_IDLE_CNT
0 0
9 10
IE_CAL_LE
G_ERR N_ERR
0 0
17 18
PP_CHKSE
CAL_RNG
L
0 0
25 26
0 0

Table 809. CHn_CONFIG field descriptions

3 4
IE_CAL_RE
SYNC
0 0
11 12
IE_CAL_DI IE_NIB_VA
AG_ERR L_ERR
0 0
19 20
FCRC_TYP FCRC_SC_
E EN
0 0
27 28
FIL_CNT[7:0]
0 0
Description
DocID027809 Rev 4
SENT Receiver (SRX)
5 6
IE_CAL_20 IE_SMSG_
_25 OFLW
0 0
13 14
IE_SMSG_ IE_FMSG_
CRC_ERR CRC_ERR
0 0
21 22
SCRC_TYP
PAUSE_EN
E
0 0
29 30
1 0
Access: RW
7
IE_FMSG_
OFLW
0
15
IE_NUM_E
DGES_ER
R
0
23
SUCC_CAL
_CHK
1
31
0
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