Flash Memory Controller; Flash Memory Array - STMicroelectronics SPC572L series Reference Manual

Embedded memories
The remaining sections give the functional details of the flash controller and flash array,
followed by the memory maps.
3.3.1

Flash memory controller

The SPC572Lx flash memory controller acts as an interface between the system bus and
the flash memory array and serves as the interface to the on-chip overlay RAM.
The flash memory controller contains a four-entry, two-way set-associative mini-cache that
delivers flash read data with a zero-wait state response on lines that reside in the cache.
Each entry contains one flash page, a 128-bit (16-byte) memory value. Read requests that
miss the cache generate the needed flash memory array access.
The flash memory controller contains configuration registers that manage flash functionality
such as read buffering in the mini-cache, access control, calibration RAM overlay
remapping, and read wait state management of the flash memory.
See Chapter 28: Flash memory controller (PFLASH
3.3.2

Flash memory array

SPC572Lx devices include a single 1.5 MBflash memory array, referred to as "main space,"
plus an independent 8 KB block of one-time-programmable (OTP) flash memory included to
support systems that require non-volatile memory for security features or system
initialization information. The independent 8 KB block is referred to as "UTEST space."
Reads of the embedded flash memory return a 128-bit page of data that may be buffered in
the mini-cache in the flash memory controller. Programming of the flash may be done by
double word (64-bits). Flash memory is erased on a block by block basis.
102/2058
Figure 4. SPC572Lx flash memory block diagram
XBAR
32
Flash Memory Controller
4-Entry, 2-Way Mini-Cache
128 Read
1.5 MB Flash Memory Array
DocID027809 Rev 4
64 Write
Controller), for details.
RM0400