Table 533. Timestamp Counter Configuration Field Descriptions - STMicroelectronics SPC572L series Reference Manual

CAN Subsystem
44.3.5.2.8 Timestamp Counter Configuration Register (TSCC)
Address: 0x0020
0 1
R
W
Reset 0 0
16 17 18
R
W
Reset 0 0
1. These are protected write (P) bits which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0
[INIT] of CCCR register are set to "1".

Table 533. Timestamp Counter Configuration field descriptions

Field
0:11 Reserved
Timestamp Counter Prescaler
0x0–0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1
12:15
to16].
The actual interpretation by the hardware of this value is such that one more than the value
TCP
programmed here is used.
Note: With CAN FD an external counter is required for timestamp generation (TSS = "10")
16:29 Reserved
Timestamp Select
00 Timestamp counter value always 0x0000
30:31
01 Timestamp counter value incremented according to TCP
TSS
10 Reserved
11 Same as "00"
1012/2058
2 3 4 5
0
0 0 0 0
19 20 21
0 0 0 0
Figure 479. Timestamp Counter Configuration Register
6 7 8 9
0 0 0 0
22 23 24 25
0
0 0 0 0
Description
DocID027809 Rev 4
10 11 12 13
TCP
0 0 0 0
26 27 28 29
0 0 0 0
RM0400
Access: RP
14 15
(1)
0 0
30 31
1
TSS
0 0