Figure 253. Flash Memory Module Structure - STMicroelectronics SPC572L series Reference Manual

Embedded Flash Memory (MP55)
Flash core
Flash array: 2 RWW partitions
— — — — — — — — — — — —
Memory interface
The Flash Memory module is designed for use in embedded MCU/SoC applications which
require high density nonvolatile memories with high-speed Read access.
The Flash array is addressable:
•
For programs – by word (32 bits) or doubleword (64 bits).
•
For reading code partitions – by half-page (128 bits).
•
For reading data partitions – by half-page (128 bits).
Multiple-word or doubleword writes to the Flash memory may be performed to fill the
program page buffer (256 bits), enabling page programming (256 bits – requiring 4
doubleword writes) and quad-page programming (1024 bits – requiring 16 doubleword
writes). Code flash memory reads always return 128 bits, although Read buffering may be
performed by the Bus Interface Unit (BIU). The address for each word retrieved within a
half-page differs from the other addresses in the half-page by address bits (3:2).
Data Flash memory reads always return 128 bits, or two consecutive doublewords of
information. The address for each word retrieved within a doubleword differs from the other
addresses by address bits (3:2).
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Figure 253. Flash memory module structure

Flash memory module
Code Flash
1.5 MB
Partition 0
Array
interface
Flash Controller
DocID027809 Rev 4
Data Flash
32 KB
Partition 1
Registers
interface
IPS bus
RM0400
HV generator
Flash
Program/Erase
Controller
Flash
registers