Decimation Filter Register Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Address offset
0x078
0x07C
0x080
0x084
0x088
0x08C
0x090
0x094
0x098–0x0CF
0x0D0
0x0D4–0x0DF
0x0E0
0x0E4
0x0E8
0x0EC
0x0F0–0x1FF
1. See register description.
2. The TAP register stores, on each filter node, the input sample data and, for the IIR type, the filter intermediary results.
37.3.2

Decimation filter register descriptions

All registers are 32-bit wide.
37.3.2.1 Decimation Filter Module Configuration Register (DECFILTER_MCR)
The Decimation Filter module configuration register provides configuration control bits for
the Decimation Filter internal logic.
Note: One must not modify this register contents when the status bit BSY is set, except for fields
FREN, FRZ and IDIS. To guarantee that BSY does not set during the read-modify-write
operation, set IDIS=1 and wait for BSY=0 beforehand.
Table 419. Block memory map(Continued)
Register
DECFILTER_TAP0 — Filter TAP
DECFILTER_TAP1 — Filter TAP 1 Register
DECFILTER_TAP2 — Filter TAP 2 Register
DECFILTER_TAP3 — Filter TAP 3 Register
DECFILTER_TAP4 — Filter TAP 4 Register
DECFILTER_TAP5 — Filter TAP 5 Register
DECFILTER_TAP6 — Filter TAP 6 Register
DECFILTER_TAP7 — Filter TAP 7 Register
Reserved
Reserved
Reserved
DECFILTER_FINTVAL — Final Integr. Value
Register
DECFILTER_FINTCNT — Final Integr. Count
Register
DECFILTER_CINTVAL — Current Integr. Value
Register
DECFILTER_CINTCNT — Current Integr. Count
Register
Reserved
DocID027809 Rev 4
Access
(2)
0 Register R
R
R
R
R
R
R
R
R
R
R
R
Decimation Filter
Reset
Section/Page
Value
0x0000_
0000
0x0000_
0000
0x0000_
0000
0x0000_
0000
37.3.2.8/823
0x0000_
0000
0x0000_
0000
0x0000_
0000
0x0000_
0000
0x0000_
37.3.2.9/824
0000
0x0000_
37.3.2.10/825
0000
0x0000_
37.3.2.11/825
0000
0x0000_
37.3.2.12/826
0000
809/2058
841