Table 254. Auxiliary Clock 2 Divider 0 Configuration Register (Cgm_Ac2_Dc0) Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Table 253. Auxiliary Clock 1 Divider 0 Configuration Register (CGM_AC1_DC0) field
Field
Divider Division Value — The resultant LFAST clock will have a period 'DIV + 1' times that of auxiliary
9–15
clock 1. If DE is set to 0 (divider 0 is disabled), any write access to the DIV field is ignored and the LFAST
DIV
clock remains disabled.
16–31 Reserved
24.3.1.22 Auxiliary Clock 2 Divider 0 Configuration Register (CGM_AC2_DC0)
This register controls auxiliary clock 2 divider 0 when the "CAN jitter" feature is not enabled (see
Section 24.4.3.1, Divider Jitter
Note: Byte and half-word write accesses are not allowed for this register. Such accesses do not
result in an exception, but the value is not loaded with the new value.
Address 0x0848
0 1 2
R 0 0
DE
W
Reset 0 0 0
16 17 18
R 0 0 0
W
Reset 0 0 0
Figure 202. Auxiliary Clock 2 Divider 0 Configuration Register (CGM_AC2_DC0)

Table 254. Auxiliary Clock 2 Divider 0 Configuration Register (CGM_AC2_DC0) field descriptions

Field
Divider Enable
0
0 Disable auxiliary clock 2 divider 0
DE
1 Enable auxiliary clock 2 divider 0
1–9 Reserved
Divider Division Value — The resultant SENT will have a period 'DIV + 1' times that of auxiliary clock 2.
10–15
If DE is set to 0 (divider 0 is disabled), any write access to the DIV field is ignored and the SENT remains
DIV
disabled.
16–31 Reserved
24.3.1.23 Auxiliary Clock 3 Select Control Register (CGM_AC3_SC)
This register is used to select the current clock source for the PLL0 reference clock.
See Figure 203 for details.
descriptions(Continued)
Injection).
Access: User read/write, Supervisor read/write, Test read/write
3 4 5 6
0 0 0 0
0 0 0 0
19 20 21 22
0 0 0 0
0 0 0 0
DocID027809 Rev 4
Clock Generation Module (MC_CGM)
Description
7 8 9 10
0 0 0
0 0 0 0
23 24 25 26
0 0 0 0
0 0 0 0
Description
11 12 13 14
DIV
0 0 0 0
27 28 29 30
0 0 0 0
0 0 0 0
515/2058
15
0
31
0
0
541