Sram Ecc Mechanism - STMicroelectronics SPC572L series Reference Manual

RAM controller (PRAM)
Offset 0x00 (PRCR1)
0 1 2 3 4
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 235. Platform RAM Configuration Register 1 (PRCR1)
Table 282. Platform RAM Configuration Register 1 field descriptions
Field
0–21 Reserved
22–23 AHB port arbitration mode
PRI 00 Round robin
01 Port p0 has priority over p1
10 Port p1 has priority over p0
11 Reserved
24 Port p1 read burst optimization disable
P1_BO_DIS 0 32-bit WRP4 read bursts are optimized such that the controller returns a 2-1-1-1 response
when PRCR[FT_DIS]=1
1 32-bit WRP4 read bursts are not optimized; the controller returns a 2-2-2-2 response when
PRCR[FT_DIS]=1
25 Port p0 read burst optimization disable
P0_BO_DIS 0 32-bit WRP4 read bursts are optimized such that the controller returns a 2-1-1-1 response
when PRCR[FT_DIS]=1
1 32-bit WRP4 read bursts are not optimized; the controller returns a 2-2-2-2 response
PRCR[FT_DIS]=1
26–30 Reserved
31 Flow through disabled
FT_DIS This field defines the AHB response of the RAM controller on reads. The state of this field has no
impact on the response latency on writes. This bit is cleared by hardware reset.
0 RAM read data is passed directly to the system bus, incurring no additional latency
1 RAM read data is registered prior to returning on the system bus, incurring 1 extra cycle of
latency
1. The number of cycles taken for a RAM access can vary ±1 clock cycle depending on the RAM speed relative to the PRAM
controller clock frequency. If system RAM is running at the same frequency as the PRAM controller a random initial access
takes 2 clock cycles. If system RAM is running at a slower frequency a random initial access may take 3 clock cycles.
Subsequent burst beats take either 1 or 2 cycles depending on RAM speed relative to PRAM controller clock frequency.
27.3

SRAM ECC mechanism

The system SRAM width organization at the RAM controller is 32-bit data + 7-bit ECC
covering address and data.
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DocID027809 Rev 4
Description
RM0400
Access: Read/write
0 0 0 0 0
1
1
(1)
1
when