Can Nodes 1 And 2 I/Os Sharing - STMicroelectronics SPC572L series Reference Manual

RM0400
buffer which is simultaneously transferred to the CAN core, inconsistent data may be
transmitted on the CAN bus.
This functionality is achieved using the "transmit buffer request pending" (M_CAN)
information of the CAN modules. With the information from these signals, the message
buffer locker prevents Host accesses from transmitting message buffers which are
requested and pending for transmission.
44.5.3.1 Transmit message buffer access locking for M-CAN
Each CAN module can have at most 32 TX Buffers and the size of each TX Buffer is 4
words. The CPU write locking mechanism ensures that whenever any TX Buffer's pending
request is set (by the TRP bit of the TXBRP register), the CPU does not get any write
access to the corresponding TX buffers. If the CPU tries to write into a TX Buffer whose
pending request is set it receives an error response on the CAN RAM Transfer Error port.
44.6

CAN nodes 1 and 2 I/Os sharing

Each CAN node has its Tx/Rx signals connected to separated GPIO pairs. It is required for
M_CAN_1 and M_CAN_2 to share one common GPIO pair. This feature is described below.
Tx
M_CAN_1
Rx
IP section
Tx
M_CAN_2
Rx
44.7 External signal description
The CAN subsystem has following external pins.
•
M_CAN_x_RX: M_CAN x receive input
• M_CAN_x_TX: M_CAN x transmit output
Figure 539. M_CAN_1 and M_CAN_2 connections to GP I/Os
DocID027809 Rev 4
M_CAN1tx_and_M_CAN2tx_o
device section
CAN Subsystem
Tx1
Rx1
Multiplexers and control
logic to be implemented
in the SIUL block
Tx2
Rx2
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