STMicroelectronics SPC572L series Reference Manual page 374

Interrupt Controller (INTC)
code to restore SRR0 and SRR1, restore working registers, and delete stack
frame (not shown)
rfi
vector_table_base_address:
address of ISR for interrupt with vector 0
address of ISR for interrupt with vector 1
.
.
.
address of ISR for interrupt with vector 1022
address of ISR for interrupt with vector 1023
ISRn:
code to service the interrupt event (not shown)
code to clear flag bit which drives interrupt request to INTC (not shown)
blr
18.7.2.2 Hardware vector mode
This interrupt exception handler is useful with processor and system bus implementations
that support a hardware vector.
interrupt_exception_handlern:
b interrupt_exception_handler_continuedn# 16 bytes available, branch to
continue
interrupt_exception_handler_continuedn:
code to create stack frame, save working register, and save SRR0 and SRR1
(not shown)
wrteei1
code to save rest of context required by Power Architecture EABI (not shown)
bl ISRn
epilog:
code to restore most of context required by Power Architecture EABI (not
shown)
374/2058
# return to epilog
# enable processor recognition of interrupts
# branch to ISR for interrupt with vector n
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