Register Classification For Safety - STMicroelectronics SPC572L series Reference Manual

SENT Receiver (SRX)
Note: The value of the CH is device-specific. See the Device Configuration chapter for details.
49.3.2.22 Channel 'n' Fast Message CRC Read Register (n = 0 to (CH-1))
(CHn_FMSG_CRC)
Address offset: 0x0164 + 0x18 × n
This is register CHn_FMSG_CRC. The contents of this register are same as
Section 49.3.2.13: DMA Fast Message CRC Read Register
49.3.2.23 Channel 'n' Fast Message Time Stamp Read Register (n = 0 to (CH-1))
(CHn_FMSG_TS)
Address offset: 0x0168 + 0x18 × n
This is register CHn_FMSG_TS. The contents of this register are same as
Section 49.3.2.14: DMA Fast Message Time Stamp Read Register
49.3.2.24 Channel 'n' Serial Message Read Register (Bit 3) (n = 0 to (CH-1))
(CHn_SMSG_BIT3)
Address offset: 0x016C + 0x18 × n
This is register CHn_SMSG_BIT3. The contents of this register are same as
Section 49.3.2.15: DMA Slow Serial Message Bit3 Read Register
Note: The value of the CH is device-specific. See the Device Configuration chapter for details.
49.3.2.25 Channel 'n' Serial Message Read Register (Bit 2) (n = 0 to (CH-1))
(CHn_SMSG_BIT2)
Address offset: 0x0170 + 0x18 × n
This is register CHn_SMSG_BIT2. The contents of this register are same as
Section 49.3.2.16: DMA Slow Serial Message Bit2 Read Register
49.3.2.26 Channel 'n' Serial Message Time Stamp Read Register (n = 0 to (CH-1))
(CHn_SMSG_TS)
Address offset: 0x0174 + 0x18 × n
This is register CHn_SMSG_TS. The contents of this register are same as
Section 49.3.2.17: DMA Slow Serial Message Time Stamp Read Register
(DMA_SMSG_TS).
49.3.3

Register Classification for Safety

The registers of this module are classified as per Safety Requirements as follows:
Safety Critical: There are no safety critical registers in this module.
Safety Relevant: The register bits/fields in this category are safety relevant as any random
error in these bits will lead to unwanted interference to CPU/DMA. The registers containing
1396/2058 DocID027809 Rev 4
(DMA_FMSG_CRC).
(DMA_FMSG_TS).
(DMA_SMSG_BIT3).
(DMA_SMSG_BIT2).
RM0400