Figure 670. Samplers, Each Sampler Has 3 Registers - STMicroelectronics SPC572L series Reference Manual

LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communications
LR Output
1 Sampler Enabled
+
1 Phase Enable
1 Sampler Enabled
+
3 Phase Enables
In order to achieve the sampler and phase enable requirements each Sampler block will
require the logic as shown in
The Clock Gating Element resides inside the Clocking Module block. The interface will
provide the enables to the Clocking Module and the Clocking Module will in return provide
the individual clocks to the sampling registers.
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Figure 670. Samplers, each Sampler has 3 Registers

Intermediate
Initial
Figure 671.
DocID027809 Rev 4
Final
High Speed 4 Phases (Phase 0, 0, 0)
Sampler 0
Low Speed 4 Phases (Phase 0, 0, 0)
High Speed 4 Phases (Disabled)
Sampler 1
Low Speed 4 Phases (Phase 1, 0, 0)
High Speed 4 Phases (Phase 2, 0, 0)
Sampler 2
Low Speed 4 Phases (Phase 2, 0, 0)
High Speed 4 Phases (Disabled)
Sampler 3
Low Speed 4 Phases (Phase 3, 0, 0)
High Speed 4 Phases (Phase 4, 2, 0)
Sampler 4
Low Speed 4 Phases (Disabled)
High Speed 4 Phases (Disabled)
Sampler 5
Low Speed 4 Phases (Disabled)
High Speed 4 Phases (Phase 6, 4, 0)
Sampler 6
Low Speed 4 Phases (Disabled)
High Speed 4 Phases (Disabled)
Sampler 7
Low Speed 4 Phases (Disabled)