Functional Description - STMicroelectronics SPC572L series Reference Manual

RM0400
65.4.6 Trace Memory fill level and partition configuration register
(NAR_AHFPAR)
This register provides the configuration to set the fill level marker for debug trace memory,
connected at the trace memory bus, to generate the partial full event indication and the
partition related configuration for main queue (internal central queue). The following figure
shows the format of the NAR_AHFPAR.
31 30 29
R 0 0
W
Reset 0 0 0
15 14 13
R 0 0
W
Reset 0 0 0
Figure 1122. Trace memory fill level and partition configuration register (NAR_AHFPAR)
The NAR_AHFPAR is described in the following table.
Field
31-11
10
AHB01kEN
9-4
3–0
AHB_01K_Marker
65.5

Functional description

High-level descriptions of the operation of the NAR and its main functional blocks are given
in the following sections.
65.5.1 Reset/Startup
Assertion of global reset causes the NAR operation to immediately cease. All queues and
configuration registers are reset. Upon exiting reset, the Nexus Port Controller (NPC) block
inside the NAR is disabled. Holding TMS high for five consecutive rising edges of TCK puts
TAP controller into the Test-Logic-Reset state regardless of the current state. This applies
reset to only TAP controller and JTAG related logic. Applying soft reset through the
NAR_CR resets the entire NAR including the TAP controller and configuration registers.
28 27
0 0 0
0 0
12 11
0 0
0
0 0
Table 1060. NAR_AHFPAR field description
Reserved and must be written with 0s
Enable 1K Marker Event
Reserved and must be written with 0s
Value at this field is used to compare a 4-bit slice of internal Trace Memory address
bus which works at boundary of 1K. A match with this value generates an event to
SPU to indicate the fill status of External Overlay Trace memory. See
Overlay and internal trace memory full status generation
Note: This is used in PD as it has memory ranges from 1K to 15K
26 25 24
0 0 0
0 0 0
10 9 8
0 0
AHB01kEN
0 0 0
Description
DocID027809 Rev 4
Nexus Aurora Router (NAR)
23 22 21 20 19
0 0 0 0 0
0 0 0
7 6 5 4 3
0 0 0 0
AHB_01K_Marker
0 0 0 0 0
18 17 16
0 0 0
0
2 1 0
0 0 0
Section 65.5.12:
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