Table 46. Dspi Registers Memory Map - STMicroelectronics SPC572L series Reference Manual

Device configuration
6.7.4.7 DSPI ITSB Mode
For the ITSB trigger, the internal DSPI trigger (TRGPRD in DSICR1) will be used. Use of
external trigger is not supported.
6.7.4.8 DSPI registers
Table 46
6.7.4.8.1 DSPIx_MCR Implementation
Figure 16
Address: Base + 0x0000
0 1
R
W
Reset 0 0
16 17
R 0
W
Reset 0 1
Figure 16. DSPI Module Configuration Register (DSPIx_MCR)
Field
Master/Slave Mode Select
0
Configures the DSPI for either master mode or slave mode.
MSTR 0 DSPI is in slave mode.
1 DSPI is in master mode.
Continuous SCK Enable
1
Enables the Serial Communication Clock (SCK) to run continuously.
CONT_SCKE 0 Continuous SCK disabled.
1 Continuous SCK enabled.
164/2058
shows the absolute addresses of DSPI module registers in this MCU.

Table 46. DSPI registers memory map

Absolute address (hex)
FFE7_0000
FFE7_8000
shows the implementation of the DSPIx_MCR in this MCU.
2 3 4 5
DCONF FRZ
0 0 0 0
18 19 20 21
0 0
0 0 0 0
Table 47. DSPIx_MCR field descriptions
DocID027809 Rev 4
6 7 8 9
0 0 0 0
22 23 24 25
0 0
SMPL_PT
0 0 0 0
Description
Module
DSPI0 registers
DSPI4 registers
Access: User read/write
10 11 12 13
PCSIS[7:0]
0 0 0 0
26 27 28 29
0 0
XSPI
0 0 1 0
RM0400
14 15
0 0
30 31
PES
0 1