Figure 417. Speb Watchpoint Control 1 Register (Gtmdi_Speb_Wpc1) - STMicroelectronics SPC572L series Reference Manual

GTM Development Interface (GTMDI)
Table 469. GTMDI_SPEA_WPC2 field descriptions(Continued)
Field
Watchpoint Trigger Enable 2. The TEN2 field controls if a watchpoint external trigger is issued by
1 the SPEA DIR selected event.
TEN2 0 Disable External Watchpoint Trigger Generation
1 Enable External Watchpoint Trigger Generation
Start/Stop Enable 2. The SEN2 bit field enable the SPEA DIR selected event to consider the
Start/Stop inputs for watchpoint trace message generation. If this bit is cleared, the messages are
0
controlled only by JTAG writes to the WMC2 field in the GTMDI_SPEA_WPC1 register.
SEN2
0 Disable trace control from Start/Stop inputs
1 Enable trace control from Start/Stop inputs
42.5.1.12 SPEB watchpoint control 1 register 1 (GTMDI_SPEB_WPC1)
The GTMDI_SPEB_WPC1 register shown in
issued by SPEB channels. These triggers are used for GTM to enter Halt state, generate
watchpoint messages and to control logic outside of the GTMDI module, such as SPU
interface.
Note: Start/Stop signals inputs to the GTMDI can overwrite the state of the WMC1 and WMC2
control bits thus controlling the Watchpoint messages behavior. In case of JTAG modifies
the WMC1 or WMC2 bits and Start/Stop signals occur at the same time also modifying the
same bits, Start/Stop signals have precedence over JTAG writes. The SEN1 and SEN2
control bits from the GTMDI_SPEB_WPC2 register need to be set in order to allow external
Start/Stop signals to control the WMC1/2 bits.
Register index: 35
31 30
R 0 0
W
RESET: 0 0
15 14
R 0 0
W
RESET: 0 0
Table 470
902/2058
29 28 27 26
0 0 0
SSEL
0 0 0 0
13 12 11 10
0 0 0 0
0 0 0 0

Figure 417. SPEB watchpoint control 1 register (GTMDI_SPEB_WPC1)

describes the GTMDI_SPEB_WPC1 register functions.
Description
Figure 417
25 24 23 22
0
WMC1
0 0 0 0
9 8 7 6
0 0 0
WMC2
0 0 0 0
DocID027809 Rev 4
controls the Watchpoint Triggers
21 20 19 18
0 0
TSS1
0 0 0 0
5 4 3 2
0 0
TSS2
0 0 0 0
RM0400
17 16
0
HEN
1
0 0
1 0
0
HEN
2
0 0