Table 124. Siul2_Mscr_Io_0–Siul2_Mscr_Io_511 Field Description - STMicroelectronics SPC572L series Reference Manual

System Integration Unit Lite2 (SIUL2)
Address: 0x0240–0x0A3C
0 1
R 0 0
W
Reset 0 0
16 17
R
INV
W
Reset 0 0
Figure 65. I/O Pin Multiplexed Signal Configuration Registers (SIUL2_MSCR_IO_0–
Table 124. SIUL2_MSCR_IO_0–SIUL2_MSCR_IO_511 field description
Field
0–1 Reserved
Output Edge Rate Control—Used only when the associated destination is a chip pin. Specifies
the driver strength of the associated pin.
00b Weak
2–3
01b Medium
OERC
10b Strong
11b Very strong
Note: Refer to the SPC572Lx I/O Signal Description and Input Multiplexing Tables
4–5 Reserved
Output Drive Control—used only when the associated destination is a chip pin. Specifies the type
of output drive control for the associated pin.
000 Output buffer disabled
001 Open-drain
5–7
010 Push-pull
ODC
011 Open-source
100 Microsecond Channel LVDS
101 LFAST LVDS
110–111 Reserved
Safe Mode Control—Used only when the associated destination is a chip pin. Specifies whether
8 the chip disables the pin's output buffer when the chip enters Safe mode.
SMC 0 Disable (the output buffer returns to its previous state when the chip leaves Safe mode)
1 Don't disable
Analog Pad Control—Used only when the associated destination is a chip pin that supports
9 analog I/O. Enables the pin's analog-input-path switch.
APC 0 Disable (the switch is off)
1 Enable (another module can control the state of the switch)
Input Level Selection—Used only when the associated destination is a chip pin. Specifies the
logic family for the associated pin, which determines its logic switching levels.
10–11
00b Automotive
ILS 01b TTL
10b LVDS
11b CMOS
298/2058
2 3 4 5
0
OERC
0 0 0 0
18 19 20 21
0 0 0 0
SIUL2_MSCR_IO_511)
DocID027809 Rev 4
6 7 8 9
ODC SMC APC
0 0 1 0
22 23 24 25
0 0 0 0
Description
Access: User read/write
10 11 12 13
ILS IBE HYS
0 0 1 0
26 27 28 29
SSS
0 0 0 0
(1)
RM0400
14 15
WPD WPU
E E
0 1
30 31
0 0