Table 38. Reference Links To Related Information - STMicroelectronics SPC572L series Reference Manual

Device configuration
Topic
Full description
System memory map
Clocking
Power management
DMA channel assignments
6.6.2.1 PIT instantiation
PIT Number of
module channels
PIT0
PIT1
6.6.2.2 PIT/DMA periodic trigger assignments
In PIT1, DMA is not supported. PIT0 generates periodic trigger events to the DMA Mux. To
check the mapping of the PIT0 channel number with the corresponding DMA channel
number, refer to the
6.6.2.3 PIT registers
Table 40
158/2058

Table 38. Reference links to related information

Related module
Direct memory access multiplexer
Table 39. PIT information
4 PIT0 has 4 standard channels. In PIT0, all registers are cleared by any reset.
PIT1 has chaining mode to implement a 64-bit timer and the timer value is
2
unchanged by a functional reset.
Table 26: DMAMUX peripheral DMA request to input source
and Table 41 show the implementation of PIT registers in this MCU.
Figure 13. PIT configuration
Peripheral bridge
Register
access
Periodic interrupt timer
PIT Chapter 41: Periodic Interrupt Timer (PIT)
— Chapter 5: Memory map
— Chapter 21: Clocking
— Chapter 9: Power management
Chapter 20: Direct Memory Access
Multiplexer (DMAMUX)
Description
DocID027809 Rev 4
RM0400
Reference
mapping.