Phase0 Phase: Analog Supply Initial Configuration - STMicroelectronics SPC572L series Reference Manual

Reset and Boot
managed by the PMC, which provides enable and status bits for these voltage detection
circuits.
The PMC sends a signal to the Reset Generation Module when power stabilization has
been achieved. The Reset Generation Module then advances to the PHASE0 state (see
Figure 23). During the power-up phase, the PMC does the following:
•
Drives to a logic '0' all LVDxx (low-voltage detect) and HVDxx (high-voltage detect)
signals monitored by the Power Management Control (PMC) module.
•
Monitors its own power supply voltage (VDD_HV_PMC) to determine that the applied
voltage is within a specified range.
•
Monitors the core power supply voltage (VDD_LV_CORE) to determine that the applied
voltage is within a specified range.
•
Monitors the low- and high-voltage detect circuit power supply voltage to determine that
the applied voltage is within a specified range.
•
Holds the outputs of the internal low- and high-voltage detect circuits at a ground state
until the PMC determines that all power supplies needed for correct device initialization
and configuration are within their respective functional voltage ranges.
•
Determines that all power supplies needed for correct device initialization and
configuration are within their respective functional voltage ranges.
•
Enables all low- and high-voltage detect circuits once all power supplies are at their
functional levels.
•
Begins to monitor the various power supplies using the high- and low-voltage detect
circuits.
•
Provides status information to the Reset Generation Module (MC_RGM) indicating
whether or not power is properly applied.
To exit power-up and enter PHASE0:
•
All enabled 'destructive' resets must be processed.
•
All power supplies must be at their functional voltages.
•
The PMC must signal the MC_RGM that all power supplies are at the required levels.
7.3.3

PHASE0 Phase: analog supply initial configuration

This phase is entered:
•
On exit from power-up phase.
•
On PORST pin falling edge detection except for the initial power-up sequence.
•
Immediately from PHASE1, PHASE2, PHASE3 or IDLE, on the occurrence of a
PORST falling edge event other than power-on reset.
During PHASE0:
•
All digital modules are reset, including safety, security, and test modules.
•
All trimming bits for analog modules are reset.
•
Startup of the internal analog modules (PMC, IRCOSC, and I/Os) begins:
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PMC determines that proper voltages are applied.
I/O pins are ensured correctly configured: outputs are driven to known levels,
inputs ignored.
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