Performance Counters/Timers Unit - STMicroelectronics SPC572L series Reference Manual

RM0400
63.6.5

Performance counters/timers unit

The 32-bit SPU counters may be used to delay events, count distances, count latencies or
count events as shown in
or a timer via the configuration register. The basic counting operation is straightforward:
once enabled (default is disabled mode), the counter increments using the platform clock
whenever the selected input is driven to a logic 1.
Access (via the JTAG interface) to each of the counter/timer registers allows the
configuration of the timer/counter, the compare registers and global SPU timer/counter
status registers. These registers are accessible via the JTAG interface even when the SPU
is in disabled mode.
Reset_n
Match_n
63.6.5.1 Counter events and actions
Each counter is capable of detecting one event condition, such as compare value match.
The compare value match is used for triggering actions in the SPU. Each counter can be
reset in response to a reset action generated from the SPU. Capture registers are available
for capturing the counter state in response to a SPU trigger condition. This capture
information is updated in the status register, which is accessible to users via JTAG interface.
These status registers are if type write 1 to clear (W1C).
There are two classes of signals, actions and events:
•
Actions—each timer/counter has an interface from the action unit to start/increment
and reset as appropriate. The start/increment signal is a single signal, with the
Figure 1101. Each counter can be configured as either a counter
Figure 1101. Counters/timers overview
Increment/Start
Timer/Counter_n[0:31]
>
Comparator_n
Compare_n[0:31]
Status Register[0:15]
DocID027809 Rev 4
Sequence Processing Unit (SPU)
Capture Action
capture value [0:15]
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