Dsmc Timing Diagram - STMicroelectronics SPC572L series Reference Manual

RM0400
30.3.1.2.3 Load-and-Set-1(Bit) (LAS1)
0 1 2 3 4
las1.b 0 1 1 0 0 0 0
las1.h 0 1 1 0 0 0
las1.w 0 1 1 0 0
This command first reads the referenced memory location; it then modifies the read operand
by setting the single bit position defined in the decoration (BIT); the modified data is then
written back to the referenced memory location and the original read data returned to the
initiating processor core.
tmp = mem[accessAddress, size] // memory read
rdata = tmp// rT = rdata = tmp
mask = 1 << (container - bit - 1)// generate bit mask
tmp = tmp | mask// modify
mem[accessAddress, size] = tmp// memory write
30.4

DSMC Timing Diagram

The following timing diagram,
store instruction which is then followed by a normal load instruction. Both decorated
instructions are read-modify-write instructions and thus they take at least two cycles to
execute. In the first cycle an ECC calculation is performed on the read data as well as the
write data. Then in the second cycle of the decorated instruction the decorated operation is
performed and if it is a decorated store, the result is merged with the read data and sent to
the write data bus along with the recalculated ECC write chkbits.
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
BIT - -
BIT - -
BIT - -
Figure 283. Decoration Format: LAS1
Figure
DocID027809 Rev 4
Decorated Storage Memory Controller (DSMC)
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284, shows a decorated load followed by a decorated
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