Packet Memory - STMicroelectronics SPC572L series Reference Manual

RM0400 LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communica-
47.7.8.5 ICLC receive interrupt
This interrupt indicates reception of a valid ICLC frame. This interrupt is asserted whenever
any of the following bits is set in the RIISR along with the corresponding enable bit mask bit
is set in the RIIER.
•
ICPONF
•
ICPOFF
•
ICTSF
•
ICTFF
•
ICRSF
•
ICRFF
•
ICTEF
•
ICTDF
•
ICCTF
•
ICLPF
•
ICTOF
•
ICPRF
•
ICPSF
•
ICPFF
Each of these bits are individually maskable. So those bits that are not required to generate
an interrupt to the processor can be masked. For details on the cause of assertion of each
bit, refer RIISR. Once the interrupt is asserted, it can be negated by clearing the
corresponding flag bit in RIISR.
47.8

Packet memory

The LFAST stores packet frames for transmission, and reads packet frames after reception.
The transmitter has its own dedicated buffer and the receiver has it own dedicated buffer,
and they are not shared between each other.
Frame Type
Data Frame
Unsolicited Frame
ICLC Frame
CTS Frame
1. Only for MCR[MSEN] = 1.
2. Only for ping response data when MCR[MSEN] = 1.
Table 691. Frames Supported by LFAST interfaces
Tx Buffer
(in bits)
38 × 32
max 6 packets
9 × 32
max 1 packet
1 × 7
(1)
max 1 packet
N/A
DocID027809 Rev 4
Rx Buffer
(in bits)
38 × 32
max 6 packets
9 × 32
max 1 packet
1 × 8
(2)
max 1 packet
N/A
Memory Type
FIFO
Registers
UNSTD[8-0], UNSRDR[8-0]
Registers
ICR, PISR
N/A
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