Peripheral Clocks - STMicroelectronics SPC572L series Reference Manual

RM0400
21.5.3.2 IRCOSC reset value
Table 215
IRCOSC registers are loaded from TEST DCF flash memory (16 MHz RCOSC_1,
16 MHz RCOSC_2, 16 MHz RCOSC_3, 16 MHz RCOSC_4) (see Device Configuration
Format Records chapter for details).
Offset
21.5.3.3 IRCOSC register write protection
The IRCOSC registers do not utilize write protection.
21.6

Peripheral clocks

Figure 163
shows the default reset value for the IRCOSC registers. The values of the
Table 215. IRCOSC register reset values
04h NT—IRCOSC Native Trimming Register
08h TT—IRCOSC Temperature Trimming Register
shows the clock distribution to the cores and peripheral modules.
DocID027809 Rev 4
Register
Clocking
Reset value
0000_0000h
0000_0000h
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