Table 681. High Speed 4 Phase Selection - Sampling Procedure - STMicroelectronics SPC572L series Reference Manual

LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communications
Phase 2
Phase 3
Phase 0
Phase 1
The auto-correlation and selection of the correct clock phase starts after the edge detection
finds a 0 to 1 transition. The high speed 4 phases from the PLL and the low speed 4 phases
(generated inside the Clocking Module) are muxed inside the clocking module. The LFAST
interface block will determine which phases are to be enabled and disabled. The only time
the interface does not choose the phases is when the Clocking Module overrides the phase
enables using COCR[SMPSEL].
The input data path can be sampled by different samplers depending on the configuration:
•
High Speed 4 Phases: Samplers 0,2,4,6
•
Low Speed 4 Phases: Samplers 0,1,2,3
Each sampler block samples the data path with a different clock phase from the Clocking
Module, and re-samples it to a intermediate phase as shown in
before re-sampling it to Phase 0. The intermediate phase is used to make static timing
between the initial phase and the final phase 0. The final phase, Phase 0 is chosen so all
the clock trees after the sampler are clocked by the same clock.
Samplers
1260/2058
Figure 669. Low speed 4 phase clock alignment example
Eye Window
Ideal Phases (0,1)

Table 681. High speed 4 phase selection - sampling procedure

Initial
Sample Phase
0 Phase 0
1 Disabled
2 Phase 2
3 Disabled
4 Phase 4
5 Disabled
6 Phase 6
7 Disabled
DocID027809 Rev 4
LR Input: Eye Diagram
LR Output: Data Transition
Table
Intermediate Sample
Phase
Phase 0
Disabled
Phase 0
Disabled
Phase 2
Disabled
Phase 4
Disabled
681, and Table 682
Final
Sample Phase
Phase 0
Disabled
Phase 0
Disabled
Phase 0
Disabled
Phase 0
Disabled