STMicroelectronics SPC572L series Reference Manual page 270

Core e200z215An3 description
Bit(s) Name
Floating-Point Available
0 Floating point unit is unavailable. The processor cannot execute floating-point
instructions, including floating-point loads, stores, and moves.
1 Floating Point unit is available. The processor can execute floating-point instructions.
18 FP
Note: For Zen z215An3, the PowerISA 2.06 floating point unit is not supported in hardware, and
Machine Check Enable
19 ME
0 Asynchronous Machine Check interrupts are disabled.
1 Asynchronous Machine Check interrupts are enabled.
Floating-point exception mode 0 (not used by Zen)
20 FE0
Note: For Zen z215An3, the PowerISA 2.06 floating point unit is not supported in hardware,
21 — Reserved
Debug Interrupt Enable
22 DE
0 Debug interrupts are disabled.
1 Debug interrupts are enabled.
Floating-point exception mode 1 (not used by Zen)
23 FE1
Note: or Zen z215An3, the PowerISA 2.06 floating point unit is not supported in hardware, thus
24:25 — Reserved
Instruction Address Space
0 The processor directs all instruction fetches to address space 0.
26 IS
1 The processor directs all instruction fetches to address space 1.
Note: For Zen z215An3, Address Spaces are not supported, thus the IS bit is ignored, but
Data Address Space
0 The processor directs all data storage accesses to address space 0.
27 DS
1 The processor directs all data storage accesses to address space 1.
Note: For Zen z215An3, Address Spaces are not supported, thus the DS bit is ignored, but
28 — Reserved
PMM Performance monitor mark bit
System software can set PMM when a marked process is running to enable statistics to be
gathered only during the execution of the marked process. MSR
29 PMM
define a state that the processor (supervisor or user) and the process (marked or unmarked)
may be in at any time. If this state matches an individual state specified in the PMLCan
Performance Monitor registers, the state for which monitoring is enabled, counting is enabled.
Recoverable Interrupt
30 RI
This bit is provided for software use to detect nested machine check exception conditions.
This bit is cleared by hardware when a Machine Check interrupt is taken.
31 — Reserved
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Table 96. MSR field descriptions(Continued)
an Illegal Instruction exception will be generated for attempted execution of PowerISA
2.06 floating point instructions regardless of the setting of FP. FP is ignored, but cleared
on exceptions.
thus FE0 is ignored, but cleared on exceptions.
FE1 is ignored, but cleared on exceptions.
cleared on exceptions.
cleared on exceptions.
DocID027809 Rev 4
Description
PR
RM0400
and MSR together
PMM