Introduction - STMicroelectronics SPC572L series Reference Manual

JTAG Data Communication (JDC)
61 JTAG Data Communication (JDC)
61.1

Introduction

The JTAG Data Communication (JDC) module provides the capability to move register data
between the IPS and JTAG domains. This facilitates communication between internal
resources that access memory mapped register space and an external tool that accesses
the JTAG port.
61.2 Overview
The JDC module consists of IPS accessible registers, JTAG accessible registers, and
associated logic to coordinate movement of data from one register domain to another.
The JDC implements the following IPS data registers, occupying separate memory space:
•
32-bit memory mapped register that can be read or written via IPS (JDC_JOUT_IPS),
and whose contents are ported out for capture into a JTAG register (JOUT) to be read
via the JTAG port.
•
32-bit memory mapped register that can only be read via IPS (JDC_JIN_IPS), and
whose contents are loaded from a JTAG register (JIN).
In addition to the data registers themselves, logic is implemented to indicate when new data
has been shifted in via the JTAG port and is ready to be read from the JDC_JIN_IPS
register, and when new data has been written to the JDC_JOUT_IPS register and is ready
to be read via the JTAG port. The state of these flags is captured into a status register
(JDC_MSR), and also provided to a JTAG register (JOUT) for tool visibility.
There is a single bus interface to port register data out to the JTAGC, and a single bus
interface to port data in from the JTAGC. The architecture is shown in
Reset
IPS Domain Logic
System Clock
Peripheral
Bus
Interrupts
1796/2058
Figure 1045. JDC block diagram
JDC_JIN_IPS
32-bit
JDC_JOUT_IPS
JDC_MSR
JDC_MCR
DocID027809 Rev 4
32-bit
JIN
32-bit JTAG Register
JOUT
(32+2)-bit JTAG Register
2-bit
RM0400
Figure 1045.
TDO
TCK
TDI
TMS
JCOMP
JTAGC