Table 133. Xbar_Prsn Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Offset: 0x0000 + n*0x100 (n = 0 to 7)
0 1
R 0
W
Reset
16 17
R 0
W
Reset
Field
0
This read-only bit is reserved and always has the value zero.
Reserved
Master 7 priority. Sets the arbitration priority for this port on the associated slave port:
000 This master has level 1 (highest) priority when accessing the slave port.
001 This master has level 2 priority when accessing the slave port.
010 This master has level 3 priority when accessing the slave port.
1–3
011 This master has level 4 priority when accessing the slave port.
M7
100 This master has level 5 priority when accessing the slave port.
101 This master has level 6 priority when accessing the slave port.
110 This master has level 7 priority when accessing the slave port.
111 This master has level 8 (lowest) priority when accessing the slave port.
4
This read-only bit is reserved and always has the value zero.
Reserved
Master 6 priority. Sets the arbitration priority for this port on the associated slave port:
000 This master has level 1 (highest) priority when accessing the slave port.
001 This master has level 2 priority when accessing the slave port.
010 This master has level 3 priority when accessing the slave port.
5–7
011 This master has level 4 priority when accessing the slave port.
M6
100 This master has level 5 priority when accessing the slave port.
101 This master has level 6 priority when accessing the slave port.
110 This master has level 7 priority when accessing the slave port.
111 This master has level 8 (lowest) priority when accessing the slave port.
8
This read-only bit is reserved and always has the value zero.
Reserved
Master 5 priority. Sets the arbitration priority for this port on the associated slave port:
000 This master has level 1 (highest) priority when accessing the slave port.
001 This master has level 2 priority when accessing the slave port.
010 This master has level 3 priority when accessing the slave port.
9–11
011 This master has level 4 priority when accessing the slave port.
M5
100 This master has level 5 priority when accessing the slave port.
101 This master has level 6 priority when accessing the slave port.
110 This master has level 7 priority when accessing the slave port.
111 This master has level 8 (lowest) priority when accessing the slave port.
2 3 4 5
M7 0
See Chip Configuration section for this device's reset values.
18 19 20 21
M3 0
See Chip Configuration section for this device's reset values.
Figure 75. Priority Registers Slave (XBAR_PRSn)

Table 133. XBAR_PRSn field descriptions

DocID027809 Rev 4
6 7 8 9
M6 0
22 23 24 25
M2 0
Description
Crossbar Switch (XBAR)
Access: Supervisor read-only
10 11 12 13
M5 0
26 27 28 29
M1 0
14 15
M4
30 31
M0
311/2058
317