Peripheral Access Control Registers (Aips_Pacrx) - STMicroelectronics SPC572L series Reference Manual

Peripheral Bridge
Field
Master trusted for writes
2
Determines whether the master is trusted for write accesses.
MTW
0 This master is not trusted for write accesses.
1 This master is trusted for write accesses.
Master privilege level
3
Determines how the privilege level of the master is determined.
MPL
0 Accesses from this master are forced to user mode.
1 Accesses from this master are not forced to user mode.
15.2.2

Peripheral Access Control Registers (AIPS_PACRx)

Each of the on-platform peripherals has a four-bit PACRn field which defines the access
levels supported by the given module. Eight PACR fields are grouped together to form a 32-
bit PACRx register.
The peripheral assignments to each PACR field are defined by the memory map slot to
which the peripherals are assigned. See
your particular device. If a peripheral is absent, the corresponding PACR field is not
implemented. Reads to the location return zeroes, and writes are ignored.
Table 137
Offset Register
0x0100 PACRA
0x0104 PACRB
0x0108 PACRC
0x010C PACRD
0x0110
0x0114 PACRF
0x0118 PACRG
0x011C PACRH
Address: 0x100–11C (AIPS_PACRA–H)
0 1 2 3
R
PACRn
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Note: The reset value of PACR0 is 0101b.
Figure 79. Peripheral Access Control Registers (AIPS_PACRA–H)
Each PACRn field is defined as shown in
320/2058
Table 136. MPROTn field descriptions(Continued)
shows the top-level structure of the PACRs.
Table 137. PACR memory map
[0:3] [4:7]
PACR0 PACR1
PACR8 PACR9 PACR10
PACR16 PACR17 PACR18
PACR24 PACR25 PACR26
PACR40 PACR41 PACR42
PACR48 PACR49 PACR50
PACR56 PACR57 PACR58
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PACR(n+1) PACR(n+2) PACR(n+3) PACR(n+4) PACR(n+5) PACR(n+6) PACR(n+7)
DocID027809 Rev 4
Description
Chapter 5: Memory map
[8:11] [12:15] [16:19]
PACR2 PACR3 PACR4
PACR11 PACR12
PACR19 PACR20
PACR27 PACR28
Reserved
PACR43 PACR44
PACR51 PACR52
PACR59 PACR60
Figure 80.
for the assignments for
[20:23] [24:27]
PACR5 PACR6
PACR13 PACR14 PACR15
PACR21 PACR22 PACR23
PACR29 PACR30 PACR31
PACR45 PACR46 PACR47
PACR53 PACR54 PACR55
PACR61 PACR62 PACR63
Access: Supervisor read/write
RM0400
[28:31]
PACR7