Table 1037. Ccoms Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Note: Counter compare values and other settings are not recommended to change
dynamically, so w1c on CCOMS should be performed in either condition:
1. Counter is in disabled state (ENABLE bit of CCTRLn set to 0).
2. SW-Reset bit (SW_RESET) is set.
Offset 0x46
31 30
R 0 0
W
Reset 0 0
15 14
R CC15 CC14 CC13 CC12 CC11 CC10 CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0
W w1c w1c
Reset 0 0
The CCOMS register fields are described in
Field
Counter n Compare.
CCn
0 Counter status is not true
1 Counter status is true
63.5.1.9.2 Counter overflow status (COS)
Whenever a counter overflow occurs, the corresponding counter overflow status register bit
is set. The bits in this register can be cleared by writing a 1 to them.
format of the COS register. All of the CO fields in the COS register have the same
description as shown in
Offset 0x47
31 30
R 0 0
W
Reset 0 0
15 14
R CO15 CO14 CO13 CO12 CO11 CO10 CO9 CO8 CO7 CO6 CO5 CO4 CO3 CO2 CO1 CO0
W w1c w1c
Reset 0 0
The COS register fields are described in
29 28 27
0 0 0
0 0 0
13 12 11
w1c w1c w1c w1c
0 0 0
Figure 1094. CCOMS register format

Table 1037. CCOMS register field descriptions

Table 1038.
29 28 27
0 0 0
0 0 0
13 12 11
w1c w1c w1c w1c
0 0 0
Figure 1095. COS register format
DocID027809 Rev 4
26 25 24 23
0 0 0 0
0 0 0 0
10 9 8 7
w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
0 0 0 0
Table 1037, where n is the counter number.
Description
26 25 24 23
0 0 0 0
0 0 0 0
10 9 8 7
w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
0 0 0 0
Table 1038, where n is the counter number.
Sequence Processing Unit (SPU)
Access: User read/write
22 21 20 19
0 0 0 0
0 0 0 0
6 5 4 3
0 0 0 0
Figure 1095
Access: User read/write
22 21 20 19
0 0 0 0
0 0 0 0
6 5 4 3
0 0 0 0
18 17 16
0 0 0
0 0 0
2 1 0
0 0 0
shows the
18 17 16
0 0 0
0 0 0
2 1 0
0 0 0
1853/2058
1863