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RM0453
Reference manual
®
STM32WL5x advanced Arm
-based 32-bit MCUs
with sub-GHz radio solution
Introduction
This document is addressed to application developers. It provides complete information on
how to use the STM32WL5x microcontrollers memory and peripherals.
STM32WL5x MCUs with integrated sub-GHZ radio operating in the 150 - 960 MHz ISM
band, belong to a family of microcontrollers with different memory sizes, packages and
peripherals.
For ordering information, mechanical and electrical device characteristics, refer to the
corresponding datasheets.
®
®
®
For information on the Arm
Cortex
-Mx cores, refer to the corresponding Arm
Technical
Reference Manuals available on http://infocenter.arm.com.
STM32WL5x microcontrollers include ST state-of-the-art patented technology.
Related documents
• STM32WL55xx STM32WL54xx datasheet (DS13293)
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32WL55xx STM32WL54xx errata sheet (ES0500).
January 2023
RM0453 Rev 5
1/1450
www.st.com
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Related Manuals for STMicroelectronics STM32WL5 Series
Summary of Contents for STMicroelectronics STM32WL5 Series
- Page 1 RM0453 Reference manual ® STM32WL5x advanced Arm -based 32-bit MCUs with sub-GHz radio solution Introduction This document is addressed to application developers. It provides complete information on how to use the STM32WL5x microcontrollers memory and peripherals. STM32WL5x MCUs with integrated sub-GHZ radio operating in the 150 - 960 MHz ISM band, belong to a family of microcontrollers with different memory sizes, packages and peripherals.
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Page 2: Table Of Contents
Contents RM0453 Contents Documentation conventions ....... . . 59 General information ......... 59 List of abbreviations for registers . - Page 3 RM0453 Contents 3.4.7 Interrupts ..........85 GTZC TZSC registers .
- Page 4 Contents RM0453 Secure system memory ........117 4.5.1 Introduction .
- Page 5 RM0453 Contents 4.10.18 FLASH CPU2 control register (FLASH_C2CR) ....147 4.10.19 FLASH secure flash start address register (FLASH_SFR) ..149 4.10.20 FLASH secure SRAM start address and CPU2 reset vector register (FLASH_SRRVR) .
- Page 6 Contents RM0453 5.7.7 Receive mode (RX) ........174 5.7.8 Active mode switching time .
- Page 7 RM0453 Contents 5.10.14 Sub-GHz radio generic CRC initial MSB register (SUBGHZ_GCRCINIRH) ........211 5.10.15 Sub-GHz radio generic CRC initial LSB register (SUBGHZ_GCRCINIRL) .
- Page 8 Contents RM0453 5.10.38 Sub-GHz radio random number register 3 (SUBGHZ_RNGR3) ..218 5.10.39 Sub-GHz radio random number register 2 (SUBGHZ_RNGR2) ..218 5.10.40 Sub-GHz radio random number register 1 (SUBGHZ_RNGR1) ..218 5.10.41 Sub-GHz radio random number register 0 (SUBGHZ_RNGR0) .
- Page 9 RM0453 Contents Power supply supervisor ........234 6.2.1 Power-on reset (POR)/power-down reset (PDR) /Brownout reset (BOR) .
- Page 10 Contents RM0453 6.6.16 PWR port H pull-down control register (PWR_PDCRH) ... 277 6.6.17 PWR CPU2 control register 1 (PWR_C2CR1) ....278 6.6.18 PWR CPU2 control register 3 (PWR_C2CR3) .
- Page 11 RM0453 Contents 7.2.21 Peripheral clocks enable ........304 Low-power modes .
- Page 12 Contents RM0453 7.4.29 RCC peripherals independent clock configuration register (RCC_CCIPR) ......... . . 342 7.4.30 RCC backup domain control register (RCC_BDCR) .
- Page 13 RM0453 Contents 8.3.3 HSEM lock procedures ........373 8.3.4 HSEM write/read/read lock register address .
- Page 14 Contents RM0453 General-purpose I/Os (GPIO) ....... . 400 10.1 GPIO introduction ......... . 400 10.2 GPIO main features .
- Page 15 RM0453 Contents 10.4.17 GPIOC output data register (GPIOC_ODR) ....418 10.4.18 GPIOC bit set/reset register (GPIOC_BSRR) ....419 10.4.19 GPIOC configuration lock register (GPIOC_LCKR) .
- Page 16 Contents RM0453 11.2.11 SYSCFG CPU1 interrupt mask register 1 (SYSCFG_IMR1) ..440 11.2.12 SYSCFG CPU1 interrupt mask register 2 (SYSCFG_IMR2) ..441 11.2.13 SYSCFG CPU2 interrupt mask register 1 (SYSCFG_C2IMR1) ..441 11.2.14 SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2) .
- Page 17 RM0453 Contents 13.4.2 DMA pins and internal signals ....... 457 13.4.3 DMA transfers .
- Page 18 Contents RM0453 14.6.3 DMAMUX request line multiplexer interrupt channel clear flag register (DMAMUX_CCFR) ........493 14.6.4 DMAMUX request generator channel x configuration register (DMAMUX_RGxCR) .
- Page 19 RM0453 Contents 16.6.13 EXTI register map ........523 Cyclic redundancy check calculation unit (CRC) .
- Page 20 Contents RM0453 18.4.1 Discontinuous mode (DISCEN) ......548 18.4.2 Programmable resolution (RES) - Fast conversion mode ..548 18.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags) .
- Page 21 RM0453 Contents 18.12.8 ADC watchdog threshold register (ADC_AWD2TR) ....582 18.12.9 ADC channel selection register (ADC_CHSELR) ....583 18.12.10 ADC channel selection register [alternate] (ADC_CHSELR) .
- Page 22 Contents RM0453 19.7.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) ......... 610 19.7.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) .
- Page 23 RM0453 Contents 21.6.1 COMP1 control and status register (COMP1_CSR) ....627 21.6.2 COMP2 control and status register (COMP2_CSR) ....629 21.6.3 COMP register map .
- Page 24 Contents RM0453 23.4.3 AES cryptographic core ........649 23.4.4 AES procedure to perform a cipher operation .
- Page 25 RM0453 Contents Public key accelerator (PKA) ....... . 695 24.1 Introduction .
- Page 26 Contents RM0453 24.7.3 PKA clear flag register (PKA_CLRFR) ......719 24.7.4 PKA RAM ..........719 24.7.5 PKA register map .
- Page 27 RM0453 Contents 25.4 TIM1 registers ..........782 25.4.1 TIM1 control register 1 (TIM1_CR1) .
- Page 28 Contents RM0453 25.4.26 TIM1 capture/compare register 6 (TIM1_CCR6) ......... . . 814 25.4.27 TIM1 alternate function option register 1 (TIM1_AF1) .
- Page 29 RM0453 Contents 26.4.5 TIM2 status register (TIM2_SR) ......873 26.4.6 TIM2 event generation register (TIM2_EGR) ....875 26.4.7 TIM2 capture/compare mode register 1 (TIM2_CCMR1) .
- Page 30 Contents RM0453 27.3.11 Using the break function ........912 27.3.12 Bidirectional break inputs .
- Page 31 RM0453 Contents 28.1 Introduction ..........945 28.2 LPTIM main features .
- Page 32 Contents RM0453 28.7.13 LPTIM register map ........971 Infrared interface (IRTIM) .
- Page 33 RM0453 Contents 31.5.3 WWDG status register (WWDG_SR) ......988 31.5.4 WWDG register map ........988 Real-time clock (RTC) .
- Page 34 Contents RM0453 32.6.10 RTC shift control register (RTC_SHIFTR) ..... 1019 32.6.11 RTC timestamp time register (RTC_TSTR) ....1020 32.6.12 RTC timestamp date register (RTC_TSDR) .
- Page 35 RM0453 Contents 33.6.11 TAMP register map ........1048 Inter-integrated circuit (I2C) interface .
- Page 36 Contents RM0453 34.7.9 I2C PEC register (I2C_PECR) ......1111 34.7.10 I2C receive data register (I2C_RXDR) ..... . . 1111 34.7.11 I2C transmit data register (I2C_TXDR) .
- Page 37 RM0453 Contents 35.8.1 USART control register 1 (USART_CR1) ..... 1165 35.8.2 USART control register 1 [alternate] (USART_CR1) ... . . 1169 35.8.3 USART control register 2 (USART_CR2) .
- Page 38 Contents RM0453 36.6 LPUART interrupts ........1228 36.7 LPUART registers .
- Page 39 RM0453 Contents 37.6 SPI interrupts ..........1280 37.7 I2S functional description .
- Page 40 Contents RM0453 38.3.9 Serial-wire debug port ........1319 38.4 Debug port (DP) registers .
- Page 41 RM0453 Contents 38.6.16 DWT CoreSight peripheral identity register 3 (DWT_PIDR3) ..1347 38.6.17 DWT CoreSight component identity register 0 (DWT_CIDR0) ..1347 38.6.18 DWT CoreSight peripheral identity register 1 (DWT_CIDR1) ..1347 38.6.19 DWT CoreSight component identity register 2 (DWT_CIDR2) .
- Page 42 Contents RM0453 38.10.3 ITM trace privilege register (ITM_TPR) ..... . . 1388 38.10.4 ITM trace control register (ITM_TCR) ......1389 38.10.5 ITM CoreSight peripheral identity register 4 (ITM_PIDR4) .
- Page 43 RM0453 Contents 38.12.3 DBGMCU CPU1 APB1 peripheral freeze register 1 (DBGMCU_APB1FZR1) ........1409 38.12.4 DBGMCU CPU2 APB1 peripheral freeze register 1 (DBGMCU_C2APB1FZR1) .
- Page 44 Contents RM0453 38.13.16 CPU2 ROM2 CoreSight peripheral identity register 2 (C2ROM2_PIDR2) ........1424 38.13.17 CPU2 ROM2 CoreSight peripheral identity register 3 (C2ROM2_PIDR3) .
- Page 45 RM0453 List of tables List of tables Table 1. Device boot mode ............63 Table 2.
- Page 46 List of tables RM0453 Table 52. Stop 1 mode ............257 Table 53.
- Page 47 RM0453 List of tables Table 104. Configuring the trigger polarity ..........547 Table 105.
- Page 48 List of tables RM0453 Table 156. Arithmetic multiplication ..........707 Table 157.
- Page 49 RM0453 List of tables Table 207. RTC input/output pins ........... . 991 Table 208.
- Page 50 List of tables RM0453 Table 260. JTAG/Serial-wire debug port pins ......... . 1314 Table 261.
- Page 51 RM0453 List of figures List of figures Figure 1. System architecture ............62 Figure 2.
- Page 52 List of figures RM0453 Figure 49. DMA block diagram ........... . 456 Figure 50.
- Page 53 RM0453 List of figures Figure 101. AES block diagram ............648 Figure 102.
- Page 54 List of figures RM0453 Figure 153. Control circuit in external clock mode 1 ........742 Figure 154.
- Page 55 RM0453 List of figures Figure 205. Counter timing diagram, internal clock divided by N......835 Figure 206.
- Page 56 List of figures RM0453 Figure 255. Complementary output with dead-time insertion....... . 911 Figure 256.
- Page 57 RM0453 List of figures Figure 301. Transfer bus diagrams for SMBus slave transmitter (SBC = 1) ....1088 Figure 302. Transfer sequence flow for SMBus slave receiver N bytes + PEC....1089 Figure 303.
- Page 58 List of figures RM0453 Figure 347. SPI block diagram............1256 Figure 348.
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Page 59: Documentation Conventions
Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of them may not be used in the current document. -
Page 60: Glossary
Documentation conventions RM0453 Glossary This section gives a brief definition of acronyms and abbreviations used in this document: • Word: data of 32-bit length. • Half-word: data of 16-bit length. • Byte: data of 8-bit length. • Option bytes: product configuration bits stored in the flash memory. •... -
Page 61: Memory And Bus Architecture
RM0453 Memory and bus architecture Memory and bus architecture The following definitions are used in this section: • CPU1 = Arm Cortex-M4 with MPU and DSP • CPU2 = Arm Cortex-M0+ with MPU When ESE = 0, CPU2 is non-secure. When ESE = 1, CPU2 is secure. System architecture The main system consists of a 32-bit multilayer AHB bus matrix that interconnects the following masters and slaves:... -
Page 62: S0: Cpu1 I-Bus
Memory and bus architecture RM0453 This architecture is shown in the figure below. Figure 1. System architecture CPU1 CPU2 DMA1 DMA2 Cortex-M4 Cortex-M0+ Flash memory FLASH arbiter SRAM1 SRAM2 AHB1 AHB2 AHB3 when remapped Bus matrix MSv60752V1 2.1.1 S0: CPU1 I-bus This bus connects the instruction bus of the CPU1 core to the bus matrix. -
Page 63: S4, S5: Dma-Bus
RM0453 Memory and bus architecture SRAM2, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the AHB3 peripherals including the APB3 peripherals. 2.1.5 S4, S5: DMA-bus These buses connect the AHB master interface of the DMAs to the bus matrix.The targets of this bus are the internal flash memory, SRAM1, SRAM2 the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the AHB3 peripherals including the APB3 peripherals. - Page 64 Memory and bus architecture RM0453 Table 1. Device boot mode (continued) Boot mode selection CPU1 aliasing space CPU2 boot User flash boot SBRV boot System flash boot SBRV boot (1)(2)(3) Hold SFI/RSS boot Hold SBRV boot System flash boot SBRV boot SRAM1 boot SBRV boot User flash boot...
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Page 65: Cpu2 Boot
SRAM memory Embedded bootloader The embedded bootloader is located in the system flash memory, programmed by STMicroelectronics during production. It is used to program the flash memory using one of the following device interfaces: • USART1 on pins PA9 and PA10 •... -
Page 66: Sram Erase
Memory and bus architecture RM0453 CPU2 system flash boot CPU2 system flash memory SFI/RSS boot can be selected via BOOT0 and BOOT1. If, after a reset, the user options are not valid and BOOT0/BOOT1 select CPU1 to boot from the main flash memory, CPU2 boots instead from the system flash memory SFI/RSS. Note: When Engi bytes are not valid, or PKA or AES is not available in the product, the SFI/RSS boot firmware install is not available. - Page 67 RM0453 Memory and bus architecture The memory protection allows the following areas to be defined within a memory: • When memory unprivileged address offset > secure address offset – Secure privileged – Flash memory only: secure privileged and unprivileged read execute only (non base thread mode) –...
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Page 68: Figure 2. Memory Protection Example
Memory and bus architecture RM0453 A memory protection example with all different areas is given in Figure 2: Memory protection example. In this example the secure privileged hide protection area is only accessible read, write, execute by the secure privileged bus masters when hide protection area access is enabled in HDPADIS bit. -
Page 69: Table 3. Memory Security And Privilege Access
RM0453 Memory and bus architecture This example show only a secure and privileged protected memory map. The security and unprivileged parameters can freely be programmed in any order as detailed below: • When HDPSA > SFSA> unprivileged watermark > unprivileged write watermark, the areas appear in the following order: –... - Page 70 Memory and bus architecture RM0453 Table 3. Memory security and privilege access (continued) SoC level memory area access Secure privileged access (2)(6) access access rd, wr rd, wr (2)(6) access access Secure unprivileged rd, wr rd, wr rd, wr (2)(6) access access Non-secure privileged...
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Page 71: Memory Organization
RM0453 Memory organization 2.6.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant. -
Page 72: Memory Map And Register Boundary Addresses
RM0453 2.6.2 Memory map and register boundary addresses Figure 3. Memory map 0xFFFF FFFF 0x5801 FFFF APB3 CPU1 CPU2 0x5801 0000 internal internal AHB3 peripherals peripherals 0x5800 0000 AHB2 0xE000 0000 0x4800 0000 AHB1 0x4802 0000 APB2 0x4001 0000 APB1 0x4000 0000 0x2000 FFFF SRAM2... -
Page 73: Table 4. Memory Map And Peripheral Register Boundary Addresses
RM0453 The table below details the boundary addresses of peripherals available in the device. Table 4. Memory map and peripheral register boundary addresses Size Boundary address Peripheral Peripheral register map (bytes) 0x5801 0400 - 0x5801 FFFF Reserved APB3 0x5801 0000 - 0x5801 03FF SUBGHZSPI Section 37.9.10: SPI/I2S register map 0x5800 40C0 - 0x5800 FFFF... - Page 74 RM0453 Table 4. Memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4260 0000 - 0x47FF FFFF Reserved AHB1 bit banding 0x4240 0000 - 0x425F FFFF 2048 K (CPU1 only) APB2 bit banding 0x4220 0000 - 0x423F FFFF 2048 K (CPU1 only)
- Page 75 RM0453 Table 4. Memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4000 B400 - 0x4000 FFFF Reserved 0x4000 B000 - 0x4000 B3FF TAMP Section 33.6.11: TAMP register map 0x4000 9C00 - 0x4000 AFFF Reserved 0x4000 9800 - 0x4000 9BFF LPTIM3...
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Page 76: Cpu1 Bit Banding
RM0453 Table 4. Memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x1FFF 7800 - 0x1FFF 7FFF Flash user options Section 4.10.21: FLASH register map 0x1FFF 7400 - 0x1FFF 77FF Flash Engi AHB3 0x1FFF 7000 - 0x1FFF 73FF Flash OTP Flash RSS and... - Page 77 RM0453 Example The following example shows how to map bit [2] of the byte located at SRAM1 address 0x2000 0300 to the alias region. The formula is then: 0x2200 6008 = 0x2200 0000 + 0x0300 * 32 + 2 * 4 Writing to address 0x2200 6008 has the same effect as a read-modify-write operation on bit [2] of the byte at SRAM1 address 0x2000 0300.
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Page 78: Global Security Controller (Gtzc)
Global security controller (GTZC) RM0453 Global security controller (GTZC) GTZC introduction This section includes the description of the two following sub-blocks: • TZSC: security controller This sub-block defines the secure/privileged state of slave peripherals. It also controls the unprivileged area size for the watermark memory peripheral controller (MPCWM). •... -
Page 79: Gtzc Functional Description
RM0453 Global security controller (GTZC) Application information The TZSC and TZIC sub-blocks can be used in one of the following ways: • programmed during secure boot only, locked and not changed afterwards • dynamically re-programmed when using specific application code or secure kernel (microvisor). -
Page 80: Gtzc Internal Signals
Global security controller (GTZC) RM0453 Figure 5. GTZC block diagram (from option bytes) GTZC TZSC tzsc_periph[n]_sec SECCFGR tzsc_periph[n]_priv PRIVCFGR tzsc_periph[n]_ sec tzsc_mpcwm[n]_priv MPCWMR (from option byte) tzsc_mpcwm[n]_ sec tzsc_ila_event TZIC tzic_ila_it n x ila_event MISR (from peripherals) tzic_ila_event MSv60799V1 3.4.2 GTZC internal signals Table 5. - Page 81 RM0453 Global security controller (GTZC) Note: Some registers have only write security protection and can be accessed read non-secure (refer to individual register descriptions). • Illegal unprivileged read write access Any unprivileged transaction trying to access a privileged resource is considered as illegal.
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Page 82: Table 6. Memory Access Error Generation
Global security controller (GTZC) RM0453 Table 6. Memory access error generation Hide protected Secure Non-secure Non-secure Secure privileged memory unprivileged privileged unprivileged memory (HDPADIS = 1) memory memory memory Memory access type Fetch Read Write Fetch Read Write Fetch Read Write Fetch Read... -
Page 83: Security Controller (Tzsc)
RM0453 Global security controller (GTZC) Table 7. Peripheral access error generation Secure Non-secure Secure privileged Non-secure unprivileged unprivileged peripheral privileged peripheral peripheral peripheral Peripheral access type Fetch Fail Fail Fail Fail Read Grant Grant Grant Grant Write Fetch Fail Fail Fail Read Illegal... -
Page 84: Security Illegal Access Controller (Tzic)
Global security controller (GTZC) RM0453 address with a length defined through GTZC_TZSC_MPCWM1_UPWWMR.LGTH[11:0]. Only the area which is also defined as unprivileged in GTZC_TZSC_MPCWM1_UPWMR.LGTH[11:0] is unprivileged writable. Note: Where n represents the target memory (1 = Flash memory, 2 = SRAM1 and 3 = SRAM2). Figure 6. -
Page 85: Interrupts
RM0453 Global security controller (GTZC) 3.4.7 Interrupts TZIC is a secure peripheral that generates systematically an illegal access event when accessed by a non-secure access. TZSC is a security-aware peripheral, meaning that secure and non-secure registers co-exist. GTZC TZSC registers All GTZC TZSC registers are accessed only by words (32-bit). -
Page 86: Gtzc Tzsc Security Configuration Register (Gtzc_Tzsc_Seccfgr1)
Global security controller (GTZC) RM0453 3.5.2 GTZC TZSC security configuration register (GTZC_TZSC_SECCFGR1) Address offset: 0x010 Reset value: 0x0000 0000 Secure write access only. A bit of this register can be written only by a secure privileged transaction, when the corresponding bit in GTZC_TZSC_PRIVCFGR1 is set to privileged. If unprivileged, the register bit can be written by secure privileged and secure unprivileged transactions. -
Page 87: Gtzc Tzsc Privileged Configuration Register (Gtzc_Tzsc_Privcfgr1)
RM0453 Global security controller (GTZC) 3.5.3 GTZC TZSC privileged configuration register (GTZC_TZSC_PRIVCFGR1) Address offset: 0x020 Reset value: 0x0000 0000 Privileged write access only. A bit of this register can be written only by a secure privileged transaction, when the corresponding bit in GTZC_TZSC_SECCFGR1 register or the flash user option is set to secure. -
Page 88: Gtzc Tzsc Unprivileged Watermark 1 Register (Gtzc_Tzsc_Mpcwm1_Upwmr)
Global security controller (GTZC) RM0453 3.5.4 GTZC TZSC unprivileged watermark 1 register (GTZC_TZSC_MPCWM1_UPWMR) Address offset: 0x130 Reset value: 0x0FFF 0000 Privileged write access only. This register can be written only by secure privileged transaction, when the corresponding flash user option FSD is configured as secure. If non-secure, this register can be written by secure privileged and non-secure privileged transaction. -
Page 89: Gtzc Tzsc Unprivileged Writable Watermark 1 Register (Gtzc_Tzsc_Mpcwm1_Upwwmr)
RM0453 Global security controller (GTZC) 3.5.5 GTZC TZSC unprivileged writable watermark 1 register (GTZC_TZSC_MPCWM1_UPWWMR) Address offset: 0x134 Reset value: 0x0FFF 0000 Privileged write access only. This register can be written only by secure privileged transaction when the corresponding flash user option FSD is configured as secure. If non-secure, this register can be written by secure privileged and non-secure privileged transaction. -
Page 90: Gtzc Tzsc Unprivileged Watermark 2 Register (Gtzc_Tzsc_Mpcwm2_Upwmr)
Global security controller (GTZC) RM0453 3.5.6 GTZC TZSC unprivileged watermark 2 register (GTZC_TZSC_MPCWM2_UPWMR) Address offset: 0x138 Reset value: 0x0FFF 0000 Privileged write access only. This register can be written only by secure privileged transaction, when the corresponding flash user option NBRSD is configured as secure. If non-secure, this register can be written by secure privileged and non-secure privileged transaction. -
Page 91: Gtzc Tzsc Unprivileged Watermark 3 Register (Gtzc_Tzsc_Mpcwm3_Upwmr)
RM0453 Global security controller (GTZC) 3.5.7 GTZC TZSC unprivileged watermark 3 register (GTZC_TZSC_MPCWM3_UPWMR) Address offset: 0x140 Reset value: 0x0FFF 0000 Privileged write access only. This register can be written only by secure privileged transaction, when the corresponding flash user option BRSD is configured as secure. If non-secure, this register can be written by secure privileged and non-secure privileged transaction. -
Page 92: Gtzc Tzsc Register Map
Global security controller (GTZC) RM0453 3.5.8 GTZC TZSC register map Table 9. GTZC TZSC register map and reset values Register Offset GTZC_TZSC_CR 0x000 Reset value 0x004 Reserved Reserved 0x00C GTZC_TZSC_ SECCFGR1 0x010 Reset value 0x014 Reserved Reserved 0x01C GTZC_TZSC_ PRIVCFGR1 0x020 Reset value 0x024... -
Page 93: Gtzc Tzic Registers
RM0453 Global security controller (GTZC) GTZC TZIC registers All GTZC TZIC registers are accessed by words (32-bit), halfwords (16-bit) and bytes (8-bit). 3.6.1 GTZC TZIC interrupt enable register 1 (GTZC_TZIC_IER1) Address offset: 0x000 Reset value: 0xFFFF FFFF when security is enabled (ESE = 1) Reset value: 0x0000 0000 when security is disabled (ESE = 0) This register can only be access by a secure privileged access for read and write. -
Page 94: Gtzc Tzic Status Register 1 (Gtzc_Tzic_Misr1)
Global security controller (GTZC) RM0453 Bit 7 DMA1IE: Illegal access event interrupt enable bit for DMA1 0: Disabled (masked) 1: Enabled (unmasked) Bit 6 FLASHIFIE: Illegal access event interrupt enable bit for FLASH interface 0: Disabled (masked) 1: Enabled (unmasked) Bit 5 PWRIE: Illegal access event interrupt enable bit for PWR 0: Disabled (masked) 1: Enabled (unmasked) - Page 95 RM0453 Global security controller (GTZC) Bit 13 PKAMF: Illegal access event interrupt status flag before masking for PKA 0: No illegal access event interrupt pending 1: Illegal access event interrupt pending Bit 12 SRAM2MF: Illegal access event interrupt status flag before masking for SRAM2 0: No illegal access event interrupt pending 1: Illegal access event interrupt pending Bit 11 SRAM1MF: Illegal access event interrupt status flag before masking for SRAM1...
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Page 96: Gtzc Tzic Interrupt Status Clear Register 1 (Gtzc_Tzic_Icr1)
Global security controller (GTZC) RM0453 3.6.3 GTZC TZIC interrupt status clear register 1 (GTZC_TZIC_ICR1) Address offset: 0x020 Reset value: 0x0000 0000 This register can only be access by a secure privileged access for read and write. A non secure or unprivileged access is ignored and return zero data and an illegal access event is generated. -
Page 97: Gtzc Tzic Register Map
RM0453 Global security controller (GTZC) Bit 4 SUBGHZSPICF: Illegal access event interrupt status flag clear bit for sub-GHz SPI 0: No action 1: Clear status flag Bit 3 RNGCF: Illegal access event interrupt status flag clear bit for RNG 0: No action 1: Clear status flag Bit 2 AESCF: Illegal access event interrupt status flag clear bit for AES 0: No action... -
Page 98: Embedded Flash Memory (Flash)
Embedded flash memory (FLASH) RM0453 Embedded flash memory (FLASH) FLASH introduction The flash memory interface manages the CPU1 AHB ICode and DCode accesses and the CPU2 AHB access to the flash memory. It implements the access arbitration between the two CPUs, the erase and program flash memory operations, the security mechanisms, and the read and write protection. -
Page 99: Empty Check
This area is reserved and contains the bootloader used to reprogram the flash memory through one of the following interfaces: USART1, USART2, I2C1, I2C2, I2C3, SPI1, SPI2S2. It is programmed by STMicroelectronics when the device is manufactured and protected against spurious write/erase operations. For further details, refer to the application note STM32 microcontroller system memory boot mode (AN2606). -
Page 100: Error Code Correction (Ecc)
Embedded flash memory (FLASH) RM0453 boot from. It prevents the system to boot from the flash main memory area when, for example, no user code is programmed. The flash main memory empty check status can be read from the EMPTY bit in the FLASH_ACR register. -
Page 101: Table 12. Number Of Wait States According To Flash Clock (Hclk3) Frequency
RM0453 Embedded flash memory (FLASH) memory clock (HCLK3) and the internal voltage range of the device (V ). Refer to CORE Section 6.1.4: Dynamic voltage scaling management. The table below shows the correspondence between wait states and frequency of the flash memory clock. -
Page 102: Adaptive Real-Time Memory Accelerator (Art Accelerator)
Embedded flash memory (FLASH) RM0453 4.3.5 Adaptive real-time memory accelerator (ART Accelerator) The proprietary adaptive real-time (ART) memory accelerator is optimized for STM32 industry-standard Arm Cortex-M4 with DSP processors. It balances the inherent performance advantage of the Cortex-M4 with DSP over flash memory technologies, which normally require the processor to wait for the flash memory at higher operating frequencies. -
Page 103: Figure 7. Sequential 16 Bits Instructions Execution
RM0453 Embedded flash memory (FLASH) The figure below shows the execution of sequential 16-bit instructions with and without prefetch when three wait states are needed to access the flash memory. Figure 7. Sequential 16 bits instructions execution WAIT WITHOUT PREFETCH WAIT ins 1 ins 2... - Page 104 Embedded flash memory (FLASH) RM0453 When the code is not sequential (branch), the instruction may not be present in the currently used instruction line or in the prefetched instruction line. In this case (miss), the penalty in terms of number of cycles is at least equal to the number of wait states. If a loop is present in the current buffer, no new access is performed.
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Page 105: Flash Program And Erase Operations
RM0453 Embedded flash memory (FLASH) are saved in a current buffer. The CPU2 pipeline is consequently stalled until the requested literal pool is provided. No data cache is available on CPU2. 4.3.6 Flash program and erase operations The embedded flash memory can be programmed using in-circuit programming or in- application programming. -
Page 106: Flash Main Memory Erase Sequences
Embedded flash memory (FLASH) RM0453 Note: FLASH_CR and FLASH_C2CR cannot be written when BSY is set respectively in FLASH_SR or FLASH_C2SR. Any attempt to write to these registers with BSY set causes the AHB bus to stall until BSY is cleared. 4.3.7 Flash main memory erase sequences The flash memory erase operation can be performed at page level (page erase) or on the... -
Page 107: Table 14. Mass Erase Overview
RM0453 Embedded flash memory (FLASH) Check and clear all error programming flags due to a previous programming. If not, PGSERR is set. Set PER and select the page to erase (PNB[6:0]) in FLASH_CR or FLASH_C2CR. Set STRT in FLASH_CR or FLASH_C2CR. Wait for BSY to be cleared in FLASH_SR or FLASH_C2SR. -
Page 108: Flash Main Memory Programming Sequences
Embedded flash memory (FLASH) RM0453 Set MER in FLASH_CR or FLASH_C2CR. Set STRT in FLASH_CR or FLASH_C2CR. Wait for BSY to be cleared in FLASH_SR or FLASH_C2SR. Note: The internal oscillator HSI16 (16 MHz) is enabled automatically when the STRT bit is set, and disabled automatically when the STRT bit is cleared, except if the HSI16 is previously enabled with HSION in the RCC_CR register. - Page 109 RM0453 Embedded flash memory (FLASH) Note: When the flash memory interface received a good sequence (a double-word), programming is automatically launched and the BSY bit is set. The internal oscillator HSI16 (16 MHz) is enabled automatically when the PG bit is set, and disabled automatically when the PG bit is cleared, except if the HSI16 is previously enabled with HSION in the RCC_CR register.
- Page 110 Embedded flash memory (FLASH) RM0453 Note: For correct operation, the firmware must guarantee that the flash page access protection is not changed during the fast programming sequence. This is between any of the 32 word writes. Note: When attempting to write in Fast programming mode while a read operation is ongoing, the programming is aborted without any system notification (no error flag is set).
- Page 111 RM0453 Embedded flash memory (FLASH) PGSERR is set if one of the following conditions occurs: – In the standard programming sequence or the fast programming sequence, a data is written when PG and FSTPG are cleared. – In the standard programming sequence or the fast programming sequence, MER and PER are not cleared when PG or FSTPG is set.
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Page 112: Table 15. Errors In Page-Based Row Programming
Embedded flash memory (FLASH) RM0453 If an error occurs during a program or erase operation, one of the following error flags is set in FLASH_SR and FLASH_C2SR: • PROGERR, SIZERR, PGAERR, PGSERR, MISSERR (program error flags) • WRPERR (protection error flag) In this case, if the error interrupt enable bit ERRIE is set in FLASH_CR or FLASH_C2CR, an interrupt is generated and the operation error flag OPERR is set in FLASH_SR and FLASH_C2SR. -
Page 113: Flash Option Bytes
RM0453 Embedded flash memory (FLASH) Note: The ICACHE and DCACHE must be flushed only when disabled (ICEN or DCEN = 0). FLASH option bytes 4.4.1 Option bytes description The option bytes can be read from the memory locations listed in the table below or from the following option byte registers: •... -
Page 114: Option Bytes Programming
Embedded flash memory (FLASH) RM0453 Table 16. Option bytes organization (continued) Address HDPSA[6:0] SFSA[6:0] 0x1FFF 7870 SNBRSA[4:0] SBRSA[4:0] SBRV[15:0] 0x1FFF 7878 OPTVAL[31:0] 0x1FFF 7FF8 1. The upper 32 bits of the double-word address contain the inverted data from the lower 32 bits. 4.4.2 Option bytes programming After a reset, the options related bits in FLASH_CR and FLASH_C2CR are write-protected. - Page 115 RM0453 Embedded flash memory (FLASH) Set the options start bit OPTSTRT in FLASH_CR. Wait for the BSY bit to be cleared. Note: Any modification of the value of one option is automatically performed by erasing user option bytes pages first, and then programming all the option bytes with the values contained in the flash option registers.
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Page 116: Table 17. Option Loading Control
Embedded flash memory (FLASH) RM0453 • For FSD and SFSA option, the value of mismatch is “flash memory completely secured”. • For BRSD, SBRSA and NBRSD, SNBRASA options, the value of mismatch is none secured (memories are erased). • For DDS option, the value of mismatch is “CPU2 debug disabled”. •... -
Page 117: Sub-Ghz Radio Spi Security
RM0453 Embedded flash memory (FLASH) 4.4.3 Sub-GHz radio SPI security When the system is secure (ESE = 1), the access to the sub-GHz radio SPI interface for the radio system can be made secure by the user option SUBGHSPISD. When secure, only the secure CPU2 has access to the sub-GHz radio SPI. -
Page 118: Flash Memory Protection
Embedded flash memory (FLASH) RM0453 RSSLIB_PFUNC->CloseExitHDP(RSSLIB_HDP_AREA1, 0x8020000); Flash memory protection The main flash memory can be protected against external accesses with the readout protection (RDP). The pages can also be protected against unwanted write (WRP) due to loss of program counter context. The write protection WRP granularity is 2 Kbytes. Apart from the RDP and WRP, the flash memory can also be protected against read and write from third parties (PCROP). - Page 119 Note: The debug feature is also disabled under reset. STMicroelectronics is not able to perform analysis on defective parts on which the level 2 protection has been set and the system is non-secure (ESE = 0). Change the readout protection level It is easy to move from level 0 to level 1 by changing the value of the RDP byte to any value (except 0xCC).
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Page 120: Table 19. Rdp Regression From Level 1 To Level 0 And Memory Erase
Embedded flash memory (FLASH) RM0453 Table 19. RDP regression from level 1 to level 0 and memory erase PCROP PCROP_RDP Comment None FLASH, SRAM1, SRAM2, PKA SRAM and backup registers mass erase Flash multiple page erase of all non-PCROP pages Partial SRAM1, SRAM2, PKA SRAM and backup registers erased (PCROP flash pages conserved) -
Page 121: Table 20. Access Status Versus Protection Level And Execution Modes
RM0453 Embedded flash memory (FLASH) Figure 8. Changing the RDP level Write options including Level 1 RDP = 0xAA 0xAA 0xCC default Write options including RDP = 0xCC Level 2 Level 0 RDP = 0xCC RDP = 0xAA Write options including RDP = 0xAA Other Options write (RDP level identical) includes:... -
Page 122: Proprietary Code Readout Protection (Pcrop)
Embedded flash memory (FLASH) RM0453 5. SRAM1, SRAM2 and PKA SRAM are erased when RDP changes from level 1 to level 0. 4.6.2 Proprietary code readout protection (PCROP) Two parts of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPUs with an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. -
Page 123: Write Protection (Wrp)
RM0453 Embedded flash memory (FLASH) Table 21: PCROP protection PCROP registers values (x = A or B) PCROP protection area PCROP1x_STRT = PCROP1x_END No PCROP1x, unprotected PCROP1x_STRT > PCROP1x_END No PCROP1x, unprotected PCROP1x_STRT < PCROP1x_END Pages from PCROP1x_STRT to PCROP1x_END are protected Note: It is recommended to align PCROP areas with the page granularity when using PCROP_RDP, or to leave free the rest of the page where PCROP zones starts or ends. -
Page 124: Cpu2 Security (Ese)
Embedded flash memory (FLASH) RM0453 Table 22: WRP protection WRPx registers values (x = A or B) WRP protection area WRP1x_STRT = WRP1x_END Page WRP1x is protected WRP1x_STRT > WRP1x_END No WRP, unprotected WRP1x_STRT < WRP1x_END Pages from WRP1x_STRT to WRP1x_END are protected Note: To validate the WRP options, the option bytes must be reloaded through the OBL_LAUNCH bit in FLASH_CR. - Page 125 RM0453 Embedded flash memory (FLASH) CPU2 secure SRAM areas SRAM1 and SRAM2 areas are only secure when the flash memory security is enabled (ESE = 1). The CPU2 secure SRAM2 and SRAM1 areas have a 1-Kbyte granularity and are defined by the secure “backup”...
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Page 126: Hide Protection Area (Hdpad)
Embedded flash memory (FLASH) RM0453 When ESE = 1 and the secure hide protection area is disabled, the CPU2 debug is enabled with the C2SWDBGEN bit after restarting OBL. However when the secure hide protection area is enabled, the CPU2 debug is disabled with the C2SWDBGEN bit and may subsequently be enabled by software. -
Page 127: Flash Interrupts
RM0453 Embedded flash memory (FLASH) When at least one PES bit is set, the following occurs: • Any ongoing program or erase operation is completed. The maximum latency for a flash program erase suspension is the maximum time for one program or erase operation to complete (see product datasheets for more information on the flash program and erase timing). -
Page 128: Register Access Protection
Embedded flash memory (FLASH) RM0453 Register access protection The user option registers may be protected by security and privilege. When the system is secure (ESE = 1) and the user option registers in the flash memory are also protected by privileged (FLASH_PRIVMODER.PRIV = 1), the flash memory secure user option bits (FSD, SFSA, BRSD, SBRSA, NBRSD, SNBRSA, SBRV, C2OPT, HDPAD, HDPSA and DDS) are secure and privileged. -
Page 129: Flash Registers
RM0453 Embedded flash memory (FLASH) 4.10 FLASH registers 4.10.1 FLASH access control register (FLASH_ACR) Address offset: 0x000 Reset value: 0x0000 0600 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EMPTY Res. Res. DCRST ICRST DCEN ICEN PRFTEN... -
Page 130: Flash Access Control Register 2 (Flash_Acr2)
Embedded flash memory (FLASH) RM0453 Bit 8 PRFTEN: CPU1 prefetch enable 0: CPU1 prefetch disabled 1: CPU1 prefetch enabled Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 LATENCY[2:0]: Latency These bits represent the ratio of the flash HCLK clock period to the flash memory access time. -
Page 131: Flash Key Register (Flash_Keyr)
RM0453 Embedded flash memory (FLASH) Bits 31:3 Reserved, must be kept at reset value. Bit 2 C2SWDBGEN: CPU2 software debug enable This bit is set and reset by software. When HDPAD = 0 (hide protection area enabled), the CPU2 software debug is disabled after a system reset. -
Page 132: Flash Status Register (Flash_Sr)
Embedded flash memory (FLASH) RM0453 Bits 31:0 OPTKEY[31:0]: Option byte key lower bits The following values must be written consecutively to unlock the flash memory option registers, enabling option byte programming/erasing operations: KEY1: 0x0819 2A3B KEY2: 0x4C5D 6E7F 4.10.5 FLASH status register (FLASH_SR) Address offset: 0x010 Reset value: 0x000X 0000 Res. - Page 133 RM0453 Embedded flash memory (FLASH) Bit 14 RDERR: PCROP read error Set by hardware when an address to be read through the D-bus belongs to a read protected area of the flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR.
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Page 134: Flash Control Register (Flash_Cr)
Embedded flash memory (FLASH) RM0453 Bit 2 Reserved, must be kept at reset value. Bit 1 OPERR: Operation error This bit is set by hardware when a flash memory operation (program/erase) completes unsuccessfully. This bit is set only if error interrupts are enabled (ERRIE = 1). This bit is cleared by writing 1. - Page 135 RM0453 Embedded flash memory (FLASH) Bit 31 LOCK: FLASH_CR lock This bit can only be set by software. When set, the FLASH_CR register is locked. This bit is cleared by hardware after detecting the unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. Bit 30 OPTLOCK: Options lock This bit can only be set by software.
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Page 136: Flash Ecc Register (Flash_Eccr)
Embedded flash memory (FLASH) RM0453 Bits 9:3 PNB[6:0]: page number selection These bits select the 2-Kbyte page to erase. 0x00: page 0 0x01: page 1 0x7F: page 127 Bit 2 MER: mass erase When set, this bit triggers the mass erase (all user pages). Bit 1 PER: page erase 0: page erase disabled 1: page erase enabled... -
Page 137: Flash Option Register (Flash_Optr)
RM0453 Embedded flash memory (FLASH) Bits 23:21 Reserved, must be kept at reset value. Bit 20 SYSF_ECC: system flash memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system flash memory. Bits 19:17 Reserved, must be kept at reset value. - Page 138 Embedded flash memory (FLASH) RM0453 Bit 31 C2BOOT_LOCK: CPU2 boot lock enable option bit This bit may be set by software at any time but a write to clear is only taken into account in one of the following conditions: - when ESE = 0 and staying in RDP level 0 - when ESE = 1 and staying in RDP level 0 by regressing FSD - when ESE = 0 and regressing RDP level from 1 to 0...
- Page 139 RM0453 Embedded flash memory (FLASH) Bit 17 IWDG_STOP: independent watchdog counter freeze in Stop mode 0: Independent watchdog counter frozen in Stop mode 1: Independent watchdog counter running in Stop mode Bit 16 IWDG_SW: independent watchdog selection 0: Hardware independent watchdog 1: Software independent watchdog Bit 15 Reserved, must be kept at reset value.
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Page 140: Flash Pcrop Zone A Start Address Register (Flash_Pcrop1Asr)
Embedded flash memory (FLASH) RM0453 4.10.9 FLASH PCROP zone A start address register (FLASH_PCROP1ASR) Address offset: 0x024 Reset value: 0xFFFF FFFF Default reset value from ST production is given. Subsequently, 0b1111 1111 1111 1111 1111 1111 XXXX XXXX, the option bits are loaded with user values from the flash memory at reset release. -
Page 141: Flash Wrp Area A Address Register (Flash_Wrp1Ar)
RM0453 Embedded flash memory (FLASH) access is ignored and an illegal access event is generated. Unprivileged read access is still allowed. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. -
Page 142: Flash Wrp Area B Address Register (Flash_Wrp1Br)
Embedded flash memory (FLASH) RM0453 Bits 31:23 Reserved, must be kept at reset value. Bits 22:16 WRP1A_END[6:0]: WRP area A end offset Contains the last 2-Kbyte page of the WRP area A. Bits 15:7 Reserved, must be kept at reset value. Bits 6:0 WRP1A_STRT[6:0]: WRP area A start offset Contains the first 2-Kbyte page of the WRP area A. -
Page 143: Flash Pcrop Zone B Start Address Register
RM0453 Embedded flash memory (FLASH) 4.10.13 FLASH PCROP zone B start address register (FLASH_PCROP1BSR) Address offset: 0x034 Reset value: 0xFFFF FFFF Default reset value from ST production is given. Subsequently, 0b1111 1111 1111 1111 1111 1111 XXXX XXXX, the option bits are loaded with user values from the flash memory at reset release. -
Page 144: Flash Ipcc Mailbox Data Buffer Address Register
Embedded flash memory (FLASH) RM0453 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PCROP1B_END[7:0] Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PCROP1B_END[7:0]: PCROP1B area end offset Contains the first 1-Kbyte page of the PCROP1B area. -
Page 145: Flash Cpu2 Access Control Register (Flash_C2Acr)
RM0453 Embedded flash memory (FLASH) 4.10.16 FLASH CPU2 access control register (FLASH_C2ACR) Address offset: 0x05C Reset value: 0x0000 0600 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ICRST Res. ICEN PRFTEN Res. - Page 146 Embedded flash memory (FLASH) RM0453 Bits 31:20 Reserved, must be kept at reset value. Bit 19 PESD: program/erase operation suspended This bit is set and reset by hardware. This bit is set when at least one PES bit in FLASH_ACR or FLASH_C2ACR is set. This bit is cleared when both PES in FLASH_ACR and FLASH_C2ACR are cleared.
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Page 147: Flash Cpu2 Control Register (Flash_C2Cr)
RM0453 Embedded flash memory (FLASH) Bit 5 PGAERR: programming alignment error This bit is set by hardware when the data to program cannot be contained in the same double-word (64-bit) flash memory in case of standard programming, or if there is a change of page during fast programming. - Page 148 Embedded flash memory (FLASH) RM0453 Res. Res. Res. Res. Res. ERRIE EOPIE Res. Res. Res. Res. Res. FSTPG Res. STRT Res. Res. Res. Res. Res. Res. PNB[6:0] Bits 31:27 Reserved, must be kept at reset value. Bit 26 RDERRIE: PCROP read error interrupt enable This bit enables the interrupt generation when RDERR in FLASH_SR is set to 1.
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Page 149: Flash Secure Flash Start Address Register (Flash_Sfr)
RM0453 Embedded flash memory (FLASH) Bit 1 PER: page erase 0: page erase disabled 1: page erase enabled Bit 0 PG: programming 0: Flash programming disabled 1: Flash programming enabled 4.10.19 FLASH secure flash start address register (FLASH_SFR) Address offset: 0x080 Reset value: 0xFFFF EFFF Default reset value from ST production is given as 0bX111 1111 XXXX XXXX 111X 1111 XXXX XXXX, the option bits are loaded with user values from the flash memory at power-on... -
Page 150: Flash Secure Sram Start Address And Cpu2 Reset Vector Register
Embedded flash memory (FLASH) RM0453 Bit 23 HDPAD: user flash memory hide protection area disable When FSD = 1, the user flash memory hide protection area is disabled whatever the value of this HDPAD bit. This bit is write protected when HDPAD = 0 and HDPADIS = 1. 0 (and FSD = 0): User flash memory hide protection area enabled. - Page 151 RM0453 Embedded flash memory (FLASH) write access privilege and can only be written by a privileged access. Unprivileged write access from is ignored and an illegal access event is generated. Unprivileged read access is still allowed. This register, except for C2OPT and SBRV bits, is further write protected by HDPADIS when HDPAD = 0.
- Page 152 Embedded flash memory (FLASH) RM0453 Bits 22:18 SBRSA[4:0]: secure “backup” SRAM2 start address This bit is write protected when HDPAD = 0 and HDPADIS = 1. When FSD = BRSD =0, SRAM2 is secure. SBRSA[4:0] contains the start address of the first 1-Kbyte page of the secure backup SRAM2 area.
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Page 153: Flash Register Map
RM0453 Embedded flash memory (FLASH) 4.10.21 FLASH register map Table 25. Flash interface register map and reset values Register Offset name LATENCY FLASH_ACR [2:0] 0x000 Reset value FLASH_ACR2 0x004 Reset value FLASH_KEYR KEYR[31:0] 0x008 Reset value FLASH_ OPTKEY[31:0] OPTKEYR 0x00C Reset value FLASH_SR 0x010... - Page 154 Embedded flash memory (FLASH) RM0453 Table 25. Flash interface register map and reset values (continued) Register Offset name FLASH_ WRP1B_END[6:0] WRP1B_STRT[6:0] WRP1BR 0x030 Reset value FLASH_ PCROP1B_STRT[7:0] PCROP1BSR 0x034 Reset value FLASH_ PCROP1B_END[7:0] PCROP1BER 0x038 Reset value FLASH_ IPCCDBA[13:0] IPCCBR 0x03C Reset value 0x040 to...
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Page 155: Sub-Ghz Radio (Subghz)
RM0453 Sub-GHz radio (SUBGHZ) Sub-GHz radio (SUBGHZ) Sub-GHz radio introduction The sub-GHz radio is an ultra-low-power sub-GHz radio operating in the 150 - 960 MHz ISM ® band. LoRa and (G)FSK modulation in transmit and receive, and BPSK/(G)MSK in transmit only, allow an optimal trade-off between range, data rate and power ®... -
Page 156: Sub-Ghz Radio Functional Description
Sub-GHz radio (SUBGHZ) RM0453 Sub-GHz radio functional description 5.3.1 General description The sub-GHz radio provides an internal processing unit to handle communication with the system CPU. Communication is handled by commands sent over the SPI interface, and a set of interrupts is used to signal events. BUSY information signals operation activity and is used to indicate when the sub-GHz radio commands cannot be received. -
Page 157: Transmitter
RM0453 Sub-GHz radio (SUBGHZ) Table 26. Sub-GHz internal input/output signals (continued) Signal name Signal type Description HSERDY Digital output HSE32 clock ready indication SUBGHZSPI Digital in/output Sub-GHz radio SPI interface BUSY Digital output BUSY signal Interrupts Digital output IRQ interrupts 5.3.3 Transmitter The transmit chain comprises the modulated output from the modem, that directly... -
Page 158: Receiver
Sub-GHz radio (SUBGHZ) RM0453 Table 27 gives the maximum transmit output power versus the V supply level. DDPA Table 27. Sub-GHz radio transmit high output power supply (V) Transmit output power (dBm) DDPA + 22 + 20 + 19 + 16 Transmitter low output power The transmit low output power up to + 15 dBm, is supported through the RFO_LP pin. -
Page 159: Rf-Pll
RM0453 Sub-GHz radio (SUBGHZ) frequency, f is the received signal and f is the intermediate frequency). The wanted signal is located at f The receiver features automatic I and Q calibration, that improves image rejection. The calibration is done automatically at startup before using the receiver, and can be requested by command (see Image calibration for specific frequency bands for more details). -
Page 160: Sub-Ghz Radio Clocks
Sub-GHz radio (SUBGHZ) RM0453 Table 29. LoRa mode intermediate frequencies Setting name Bandwidth [kHz] [kHz] LORA_BW_500 LORA_BW_250 LORA_BW_125 LORA_BW_62 62.5 LORA_BW_41 41.67 LORA_BW_31 31.25 LORA_BW_20 20.83 LORA_BW_15 15.63 LORA_BW_10 10.42 LORA_BW_7 7.81 Sub-GHz radio clocks 5.4.1 Internal oscillators The following sub-GHz radio dedicated internal RC oscillators are available: •... -
Page 161: Sub-Ghz Radio Modems
RM0453 Sub-GHz radio (SUBGHZ) The sub-GHz radio, depending on the transmit output power (max + 22 dBm), can heat up the device. The heating depends on the used transmit output power and the device package. Careful PCB design using thermal heat dissipation techniques must be applied to avoid heat transfer to the HSE32 reference clock source. -
Page 162: Table 30. Spreading Factor, Chips/Symbol And Lora Snr
Sub-GHz radio (SUBGHZ) RM0453 Spreading factor (SF) The LoRa spread spectrum modulation is performed by representing each data bit of the packet payload by multiple chips of information. The rate at which the spread information is sent, is referred to as the symbol rate (Rs). The ratio between the nominal data rate and the chip rate is the spreading factor (SF). -
Page 163: Lora Framing
RM0453 Sub-GHz radio (SUBGHZ) A higher coding rate provides better immunity to interference at the expense of longer transmission time. In normal conditions and factor of 4 / 5 provides the best trade off. In case of strong interference, a higher coding rate may be used. The coding rate and overhead ratio is given in the table below. -
Page 164: Figure 12. Lora Packet Frames Format
Sub-GHz radio (SUBGHZ) RM0453 The LoRa packet frames are illustrated in the figure below. Figure 12. LoRa packet frames format Explicit packet frame n preamble symbols n header symbols Preamble Header + CRC Payload CR defined by coding rate CR = 4/8 SF defined by spreading factor Implicit packet frame n preamble symbols... -
Page 165: Fsk Modem
RM0453 Sub-GHz radio (SUBGHZ) Implicit header mode In certain operation modes where the payload coding rate and CRC presence are fixed or known in advance, it can be advantageous to reduce transmission time by invoking implicit header mode. In this mode, the header is not present in the packet frame. The payload length, forward error correction coding rate and presence of the payload CRC must be configured on both sides of the sub-GHz radio link. -
Page 166: Msk Modem
Sub-GHz radio (SUBGHZ) RM0453 index. An optional Gaussian filter can be used. All modulation parameters are set using Set_ModulationParams() command. The bit rate (or equivalent chip) is referenced to the HSE32 frequency and controlled by the BR parameter, defined as follows: BR = 32 x HSE32 / BitRate where HSE32 = 32 MHz... -
Page 167: Figure 13. Generic Packet Frames Format
RM0453 Sub-GHz radio (SUBGHZ) The generic packet frames are illustrated in the figure below. Figure 13. Generic packet frames format Variable length generic packet frame Address Preamble Syncword Length Payload 0 to 1 byte 8 to 65535 bits 0 – 8 bytes 1 to 255 bytes 0 to 2 bytes CRC check... -
Page 168: Bpsk Modem
Sub-GHz radio (SUBGHZ) RM0453 Variable length generic packet mode When the packet is of uncertain or variable length, the information on the payload length must be transmitted within the packet. For this, a header with the payload length information is transmitted after the syncword. Fixed length generic packet mode In certain operation modes where the payload length is fixed or known in advance, it may be advantageous to reduce transmission time by invoking fixed length generic packet mode. -
Page 169: Bpsk Framing
RM0453 Sub-GHz radio (SUBGHZ) 5.5.7 BPSK framing The BPSK packet framing is used with the BPSK modem. The BPSK packet framing can be configured by Set_PacketParams() command and allows the total frame length definition. The full packet (preamble, synch word, device id to CRC) must be provided in the transmit data buffer. -
Page 170: Receive Data Buffer Operation
Sub-GHz radio (SUBGHZ) RM0453 from the receive data buffer, the offset must be set to the RxBufferPointer value. To write to the first byte in the transmit data buffer, the offset must be set to the TxBaseAddr value. The RAM data buffer has a circular nature: any address increment exceeding 0xFF wraps around to address 0x00. -
Page 171: Figure 15. Sub-Ghz Radio Operating Modes
RM0453 Sub-GHz radio (SUBGHZ) – RC 64 kHz and timers can be kept running (optional) – Optional registers and data memory retained • Calibration mode – intermediate mode between Deep-Sleep or Sleep, and Standby – used to calibrate the sub-GHz radio RC 64 kHz, sub-GHz radio RC 13 MHz, RF- PLL, RF-ADC and image •... -
Page 172: Startup Mode
Sub-GHz radio (SUBGHZ) RM0453 5.7.1 Startup mode At POR or after a sub-GHz radio reset, the Startup mode is entered. BUSY is set. When internal supply and clocks become available, the sub-GHz radio enters Sleep mode. 5.7.2 Sleep mode In Sleep mode, only the sub-GHz radio startup and Sleep control is operational and the configuration is lost. -
Page 173: Standby Mode
RM0453 Sub-GHz radio (SUBGHZ) When in Standby mode, the calibration of different blocks can be requested by Calibrate() command. Image calibration for specific frequency bands The image calibration is performed as part of the calibration process, by default in the band 902 - 928 MHz. -
Page 174: Receive Mode (Rx)
Sub-GHz radio (SUBGHZ) RM0453 When entering TX mode, BUSY is set. In TX mode, BUSY is cleared when the PA ramped up and preamble transmission starts. PA ramping The PA ramping time can be selected while setting the output power, by Set_TxParams(). 5.7.7 Receive mode (RX) The RX mode can be requested to be entered from Standby mode. -
Page 175: Sub-Ghz Radio Spi Interface
RM0453 Sub-GHz radio (SUBGHZ) BUSY timing is shown in the figure below. Figure 16. Sub-GHz radio BUSY timing BUSY Opcode Param 1 Param n Write command SWMODE MSv64330V1 For the different mode transitions, typical busy timing values are given in the table below. Table 33. -
Page 176: Sub-Ghz Radio Command Structure
Sub-GHz radio (SUBGHZ) RM0453 For each access, the sub-GHz radio SPI NSS goes low at the start of the transfer and is set high at the end, after all bytes have been transfered. The following transaction types are supported: • configuration transaction: provides the CPU with a direct access to control registers. - Page 177 RM0453 Sub-GHz radio (SUBGHZ) byte 3 bits 7:0 Data0[7:0]: data to write to first address byte n+3 bits 7:0 Datan[7:0]: data to write to address + n (n = number of bytes to write) Read_Register() command Read_Register(Addr, Status, Data0, Data1, to Datan) allows a block of bytes to be read in a contiguous memory area starting from the specified address.
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Page 178: Operating Mode Commands
Sub-GHz radio (SUBGHZ) RM0453 offset. The offset is auto incremented after each byte. When the offset exceeds the value 255, it is wrapped around to 0 (providing a 256 byte circular buffer). Opcode Offset[7:0] Status[7:0] Data0[7:0] Datan[7:0] byte 0 bits 7:0 Opcode: 0x1E byte 1 bits 7:0 Offset[7:0]: first read address offset byte 2... - Page 179 RM0453 Sub-GHz radio (SUBGHZ) Set_Standby() command Set_Standby(StandbyCfg) is used to set the sub-GHz radio in Standby mode. The StandbyCfg parameter allows some optional functions to be selected in Standby mode. Opcode StandbyCfg byte 0 bits 7:0 Opcode: 0x80 byte 1 bits 7:1 Reserved, must be kept at reset value.
- Page 180 Sub-GHz radio (SUBGHZ) RM0453 Set_Rx() command Set_Rx(Timeout) is used to set the sub-GHz radio in Receive mode. Opcode Timeout[23:0] byte 0 bits 7:0 Opcode: 0x82 bytes 3:1 bits 23:0 Timeout[23:0]: Transmit packet timeout 0x000000: timeout disabled 0x000001 - 0xFFFFFE: timeout enabled, single packet receive mode, resolution 15.625 μs 0xFFFFFF: timeout disabled, continuous receive mode Time-out duration is computed by the following formula:...
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Page 181: Figure 17. Receiver Listening Mode Timing
RM0453 Sub-GHz radio (SUBGHZ) The following steps are performed: Save sub-GHz radio configuration. Enter Receive mode and listen for a preamble for the specified RxPeriod period. Upon the detection of a preamble, the RxPeriod timeout is stopped and restarted with the value 2 x RxPeriod +SleepPeriod. - Page 182 Sub-GHz radio (SUBGHZ) RM0453 Set_Cad() command Set_Cad() is used to detect the channel activity and can only be used with LoRa packet types. The channel activity detection (CAD) is a specific LoRa operation mode, where the sub-GHz radio searches for a LoRa radio signal. After the search is completed, the Standby mode is automatically entered, CAD is done and IRQ is generated.
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Page 183: Sub-Ghz Radio Configuration Commands
RM0453 Sub-GHz radio (SUBGHZ) 5.8.4 Sub-GHz radio configuration commands Set_PacketType() command Set_PacketType(PktType) allows the selection of packet frame format. This command must be the first command of a sub-GHz radio configuration sequence. Changing from one sub-GHz radio configuration to another is done using Set_PacketType(). - Page 184 Sub-GHz radio (SUBGHZ) RM0453 Set_RfFrequency() command Set_RfFrequency(RfFreq) is used to lock the RF-PLL frequency to the transmit and receive frequency. Opcode RfFreq[31:0] byte 0 bits 7:0 Opcode: 0x86 bytes 4:1 bits 31:0 RfFreq[31:0]: RF frequency RF-PLL frequency = 32e x RFfreq / 2 Set_TxParams() command Set_TxParams(Power, RampTime) is used to set the transmit output power and the PA ramp-up time.
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Page 185: Table 35. Pa Optimal Setting And Operating Modes
RM0453 Sub-GHz radio (SUBGHZ) Set_PaConfig() command Set_PaConfig(PaDutyCycle, HpMax, PaSel, 0x01) is used to customize the maximum output power and PA efficiency. Opcode PaDutyCycle[2:0] HpMax[2:0] PaSel 0x01 byte 0 bits 7:0 Opcode: 0x95 byte 1 bits 7:3 Reserved, must be kept at reset value. bits 2:0 PaDutyCycle[2:0]: PA duty cycle (conduit angle) control Duty cycle = 0.2 + 0.04 x PaDutyCycle[2:0] (see Table 35... - Page 186 Sub-GHz radio (SUBGHZ) RM0453 Set_TxRxFallbackMode() command Set_TxRxFallbackMode(FallbackMode) defines the operating mode to enter after a successful packet transmission or packet reception. Opcode FallbackMode[7:0] byte 0 bits 7:0 Opcode: 0x93 byte 1 bits 7:0 FallbackMode[7:0]: Fall-back mode after successful packet transmission or packet reception 0x20: Standby mode entry (default) 0x30: Standby with HSE32 enabled mode entry...
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Page 187: Table 36. Recommended Cad Configuration Settings
RM0453 Sub-GHz radio (SUBGHZ) byte 4 bits 7:1 Reserved, must be kept at reset value. Bit 0 CadExitMode: defines the sub-GHz radio operating mode to enter after CAD scan is finished 0: Standby with RC 13 MHz mode entry after CAD, whatever is detected during the CAD scan 1: Standby with RC 13 MHz mode after CAD if no LoRa symbol is detected during the CAD scan... - Page 188 Sub-GHz radio (SUBGHZ) RM0453 type in Set_PacketType() sent prior to this function, the parameters for generic packets are interpreted as follows: • Br and Fdev are used for the transmission and reception. • Bw is used only for reception. • PulseShape represents the Gaussian filter that can be used to filter the modulation stream at the transmitter.
- Page 189 RM0453 Sub-GHz radio (SUBGHZ) bytes5 bit 7:0 Bw[7:0]: Bandwidth 0x1F: BW4 4.8 kHz DSB 0x17: BW5 5.8 kHz DSB 0x0F: BW7 7.3 kHz DSB 0x1E: BW9 9.7 kHz DSB 0x16: BW11 11.7 kHz DSB 0x0E: BW14 14.6 kHz DSB 0x1D: BW19 19.5 kHz DSB 0x15: BW23 23.4 kHz DSB 0x0D: BW29 29.3 kHz DSB 0x1C: BW39 39.0 kHz DSB...
- Page 190 Sub-GHz radio (SUBGHZ) RM0453 byte 2 bits 7:0 Bw[7:0]: Bandwidth 0x00: bandwidth 7 (7.81 kHz) 0x08: bandwidth 10 (10.42 kHz) 0x01: bandwidth 15 (15.63 kHz) 0x09: bandwidth 20 (20.83 kHz) 0x02: bandwidth 31 (31.25 kHz) 0x0A: bandwidth 41 (41.67 kHz) 0x03: bandwidth 62 (62.50 kHz) 0x04: bandwidth 125 (125 kHz) 0x05: bandwidth 250 (250 kHz)
- Page 191 RM0453 Sub-GHz radio (SUBGHZ) Generic Set_PacketParams() command Set_PacketParams(PbLength,PbDetLength,SynchWordLength,AddrComp, PktType,PayloadLength,CrcType,Whitening) is used to configure the packet handling for the sub-GHz radio. When the generic packet is selected with packet type in Set_PacketType() sent prior to this function, the parameters are interpreted as below. Opcode PbLength[15:0] PktType...
- Page 192 Sub-GHz radio (SUBGHZ) RM0453 byte 8 bits 7:3 Reserved, must be kept at reset value. bits 2:0 CrcType[2:0]: CRC type definition The CRC initialization value is provided in SUBGHZ_GCRCINIRL and SUBGHZ_GCRCINIRH. The polynomial is defined in SUBGHZ_GCRCPOLRL and SUBGHZ_GCRCPOLRH. 0x0: 1-byte CRC 0x1: no CRC 0x2: 2-byte CRC 0x4: 1-byte inverted CRC...
- Page 193 RM0453 Sub-GHz radio (SUBGHZ) byte 6 bits 7:1 Reserved, must be kept at reset value. bit 0 InvertIQ: IQ setup 0: standard IQ setup 1: inverted IQ setup BPSK Set_PacketParams() command Set_PacketParams(PayloadLength) is used to configure the packet handling for the sub-GHz radio.
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Page 194: Communication Status Information Commands
Sub-GHz radio (SUBGHZ) RM0453 5.8.5 Communication status information commands Get_Status() command Get_Status(Status) can be issued at any time. Opcode Status[7:0] byte 0 bits 7:0 Opcode: 0xC0 byte 1 bit 7 Reserved, must be kept at reset value. bits 6:4 Status_Mode[2:0] sub-GHz radio operating mode 0x2: Standby mode with RC 13 MHz 0x3: Standby mode with HSE32 0x4: FS mode... - Page 195 RM0453 Sub-GHz radio (SUBGHZ) (G)FSK Get_PacketStatus() command Get_PacketStatus(Status, RxStatus, RssiSync, RssiAvg) returns information on the last received packet. Depending on the selected packet type in Set_PacketType() sent prior to this function, the parameters for generic packets are interpreted as below. Opcode Status[7:0] RxStatus[7:0]...
- Page 196 Sub-GHz radio (SUBGHZ) RM0453 Get_RssiInst() command Get_RssiInst(Status, RssiInst) returns the instantaneous signal strength during packet reception. Opcode Status[7:0] RssiInst[7:0] byte 0 bits 7:0 Opcode: 0x15 byte 1 bits 7:0 Status[7:0]: see Get_Status() command byte 2 bits 7:0 RssiInst[7:0]: instantaneous RSSI level at the reception time Signal power = - RssiInst / 2 (in dBm) (G)FSK Get_Stats() command Get_Stats(Status, NbPktReceived, NbPktCrcError, NpPktLengthError)
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Page 197: Irq Interrupt Commands
RM0453 Sub-GHz radio (SUBGHZ) bytes 7:6 bits 15:0 NbPktHeaderError[15:0]: Number of packets received with a header CRC error Reset_Stats() command Reset_Stats(0x00,0x00,0x00,0x00,0x00,0x00) resets the received packet statistics as reported in Get_Stats() (NbPktReceived, NbPktCrcError, NbPktlengthError and NbPktHeaderError). Opcode 0x00 0x00 0x00 0x00 0x00 0x00 byte 0... - Page 198 Sub-GHz radio (SUBGHZ) RM0453 Table 37. IRQ bit mapping and definition (continued) Source Description Packet type Operation CadDone Channel activity detection finished LoRa CadDetected Channel activity detected LoRa Timeout RX or TX timeout LoRa and GFSK Rx and Tx 15:10 Not applicable Reserved Not applicable...
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Page 199: Miscellaneous Commands
RM0453 Sub-GHz radio (SUBGHZ) Clr_IrqStatus() command Clr_IrqStatus(ClrIrq) clears the IRQ status flags (IrqStatus[15:0]). Opcode ClrIrq[15:0] byte 0 bits 7:0 Opcode: 0x02 bytes 2:1 bits 15:0 ClrIrq[15:0]: Clear interrupt status Table 37 for interrupt bit map definition. For each bit: 0: no action 1: IRQ pending status flag cleared 5.8.7 Miscellaneous commands... -
Page 200: Table 38. Image Calibration For Ism Bands
Sub-GHz radio (SUBGHZ) RM0453 byte 1 bit 7 Reserved, must be kept at reset value. bit 6 CalibCfg_Image: Image calibration 0: Image calibration disabled 1: Image calibration enabled bit 5 CalibCfg_AdcBulkP: RF-ADC bulk P calibration 0: RF-ADC bulk P calibration disabled 1: RF-ADC bulk P calibration enabled bit 4 CalibCfg_AdcBulkN: RF-ADC bulk N calibration 0: RF-ADC bulk N calibration disabled... - Page 201 RM0453 Sub-GHz radio (SUBGHZ) Opcode CalFreq1[7:0] CalFreq2[7:0] byte 0 bits 7:0 Opcode: 0x98 byte 1 bits 7:0 CalFreq1[7:0]: Lower frequency of the band to calibrate (see Table byte 2 bits 7:0 CalFreq2[7:0]: Higher frequency of the band to calibrate (see Table The calibration frequencies are computed as follows: Calibration...
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Page 202: Set_Tcxomode Command
Sub-GHz radio (SUBGHZ) RM0453 byte 0 bits 7:0 Opcode: 0x17 byte 1 bits 7:0 Status[7:0]: see Get_Status() command bytes 3:2 bits 15:9 Reserved, must be kept at reset value. bit 8 OpError_PaRampError: PA ramping failed bit 7 Reserved, must be kept at reset value. bit 6 OpError_PllLockError: RF-PLL locking failed bit 5 OpError_XoscStartError: HSE32 clock startup failed bit 4 OpError_ImageCalibrationError: Image calibration failed... -
Page 203: Sub-Ghz Radio Commands Overview
RM0453 Sub-GHz radio (SUBGHZ) The definition of RegTcxoTrim and Timeout bytes is given in the table below. Table 40. RegTcxoTrim and Timeout bytes definition Byte 1 [7:3] Byte 1 RegTcxoTrim[2:0 ] (V) Byte 2-4 [23:0] timeout 0x0 = 1.6 0x000000 = timeout disabled 0x1 = 1.7 Other = timeout enabled 0x2 = 1.8... - Page 204 Sub-GHz radio (SUBGHZ) RM0453 Table 41. Sub-GHz radio SPI commands overview (continued) Command Opcode Parameters 0xC0 Status Get_Status() 0x1E Offset, Status, Data0, Data1, ..., Datan Read_Buffer() 0x1D Addr, Status, Data0, Data1, ..., Datan Read_Register() 0x00 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 Reset_Stats() 0x8F TxBaseAddr, RxBaseAddr...
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Page 205: Sub-Ghz Radio Application Configuration
RM0453 Sub-GHz radio (SUBGHZ) Sub-GHz radio application configuration The sub-GHz radio is controlled via the SPI command interface. The following sections describe the basic sequence for some sub-GHz radio operations. After releasing the sub-GHz radio reset and waking it up with sub-GHz radio SPI NSS, the sub-GHz radio automatically performs a calibration and enters Standby mode. -
Page 206: Basic Sequence For Lora And (G)Fsk Receive Operation
Sub-GHz radio (SUBGHZ) RM0453 5.9.2 Basic sequence for LoRa and (G)FSK receive operation The sub-GHz radio can be set in LoRa or (G)FSK receive operation mode with the following steps: Define the location where the received payload data must be stored in the data buffer, with Set_BufferBaseAddress(). -
Page 207: Basic Sequence For Bpsk Transmit Operation
RM0453 Sub-GHz radio (SUBGHZ) 5.9.3 Basic sequence for BPSK transmit operation The sub-GHz radio can be set in BPSK transmit operation mode by the following steps: Define the location of the transmit payload data in the data buffer, with Set_BufferBaseAddress() Write the packet data (synchronization word, payload data) to the transmit data buffer with Write_Buffer(). -
Page 208: Sub-Ghz Radio Ramp-Up Lsb Register (Subghz_Ram_Rampupl)
Sub-GHz radio (SUBGHZ) RM0453 5.10.2 Sub-GHz radio ramp-up LSB register (SUBGHZ_RAM_RAMPUPL) Address offset: 0x0F1 Reset value: 0x00 RAMPUP[7:0] Bits 7:0 RAMPUP[7:0]: Ramp-up LSB bits 5.10.3 Sub-GHz radio ramp-down MSB register (SUBGHZ_RAM_RAMPDNH) Address offset: 0x0F2 Reset value: 0x00 RAMPDN[15:8] Bits 7:0 RAMPDN[15:8]: Ramp-down MSB bits 5.10.4 Sub-GHz radio ramp-down LSB register (SUBGHZ_RAM_RAMPDNL) -
Page 209: Sub-Ghz Radio Frame Limit Lsb Register (Subghz_Ram_Frameliml)
RM0453 Sub-GHz radio (SUBGHZ) 5.10.6 Sub-GHz radio frame limit LSB register (SUBGHZ_RAM_FRAMELIML) Address offset: 0x0F5 Reset value: 0x00 FRAMELIML[7:0] Bits 7:0 FRAMELIML[7:0]: frame limit LSB bits 5.10.7 Sub-GHz radio generic bit synchronization register (SUBGHZ_GBSYNCR) Address offset: 0x6AC Reset value: 0x00 This register must be cleared to 0x00 when using packet types other than LoRa. -
Page 210: Sub-Ghz Radio Generic Cfo Lsb Register (Subghz_Gcforl)
Sub-GHz radio (SUBGHZ) RM0453 Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 DEMOD_CFO[3:0]: actual frequency error from normalized value (MSB bits) 5.10.9 Sub-GHz radio generic CFO LSB register (SUBGHZ_GCFORL) Address offset: 0x6B1 Reset value: 0x00 DEMOD_CFO[7:0] Bits 7:0 DEMOD_CFO[7:0]: actual frequency error from normalized value (LSB bits) 5.10.10 Sub-GHz radio generic packet control 1 register (SUBGHZ_GPKTCTL1R) -
Page 211: Sub-Ghz Radio Generic Whitening Lsb Register
RM0453 Sub-GHz radio (SUBGHZ) Bit 4 CONTTX: Generic packet continuous transmit enable Bits 3:2 INFSEQSEL[1:0]: Generic packet infinite sequence selection 00: preamble 0x5555 01: all zero 0x0000 10: all one 0xFFFF 11: PRBS9 Bit 1 INFSQEQEN: Generic packet infinite sequence enable Bit 0 WHITEINI[8]: Generic packet whitening initial value MSB bit [8] 5.10.12 Sub-GHz radio generic whitening LSB register... - Page 212 Sub-GHz radio (SUBGHZ) RM0453 5.10.15 Sub-GHz radio generic CRC initial LSB register (SUBGHZ_GCRCINIRL) Address offset: 0x6BD Reset value: 0x0F CRCINI[7:0] Bits 7:0 CRCINI[7:0]: Generic packet CRC initial polynomial LSB bits [7:0] These bits are used for CRC initialization. 5.10.16 Sub-GHz radio generic CRC polynomial MSB register (SUBGHZ_GCRCPOLRH) Address offset: 0x6BE Reset value: 0x10...
- Page 213 RM0453 Sub-GHz radio (SUBGHZ) 5.10.18 Sub-GHz radio generic synchronization word control register 0 (SUBGHZ_GSYNCR0) Address offset: 0x6C0 Reset value: 0x97 SYNCWORD[63:56] Bits 7:0 SYNCWORD[63:56]: Eight byte of generic packet synchronization word 5.10.19 Sub-GHz radio generic synchronization word control register 1 (SUBGHZ_GSYNCR1) Address offset: 0x6C1 Reset value: 0x23...
- Page 214 Sub-GHz radio (SUBGHZ) RM0453 5.10.22 Sub-GHz radio generic synchronization word control register 4 (SUBGHZ_GSYNCR4) Address offset: 0x6C4 Reset value: 0x56 SYNCWORD[31:24] Bits 7:0 SYNCWORD[31:24] Fourth byte of generic packet synchronization word 5.10.23 Sub-GHz radio generic synchronization word control register 5 (SUBGHZ_GSYNCR5) Address offset: 0x6C5 Reset value: 0x53...
- Page 215 RM0453 Sub-GHz radio (SUBGHZ) 5.10.26 Sub-GHz radio generic node address register (SUBGHZ_GNODEADR) Address offset: 0x6CD Reset value: 0x00 NODEADD[7:0] Bits 7:0 NODEADD[7:0]: Node address used in FSK mode register 5.10.27 Sub-GHz radio generic broadcast address register (SUBGHZ_GBCASTADDR) Address offset: 0x6CE Reset value: 0x00 BCASTADD[7:0] Bits 7:0 BCASTADD[7:0]: Broadcast address used in FSK mode register...
- Page 216 Sub-GHz radio (SUBGHZ) RM0453 5.10.30 Sub-GHz radio synchro timeout register (SUBGHZ_LSYNCTIMEOUTR) Address offset: 0x706 Reset value: 0x00 SYNCTIMEOUT[7:0] Bits 7:0 SYNCTIMEOUT[7:0]: TimeoutValue = synchtimeout[7:3]*2^(2*synchtimeout[2:0]+1) If a detection has not occurred by TimeoutValue, it goes back to Standby mode, or restart synch in continuous receive mode Bits 7:3 synchtimeout(7:3) mantissa part Bits 2:0 synchtimeout(2:0) exponent part...
- Page 217 RM0453 Sub-GHz radio (SUBGHZ) Bits 7:0 SYNCWORD[15:8]: LoRa synchronization word MSB bits [15:8] 0x14: LoRa private network 0x34: LoRa public network Others: reserved 5.10.34 Sub-GHz radio LoRa synchronization word LSB register (SUBGHZ_LSYNCRL) Address offset: 0x741 Reset value: 0x24 SYNCWORD[7:0] Bits 7:0 SYNCWORD[7:0]: LoRa synchronization word LSB bits [7:0] 0x24: LoRa private network 0x44: LoRa public network Others: reserved...
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Page 218: Sub-Ghz Radio Random Number Register 3 (Subghz_Rngr3)
Sub-GHz radio (SUBGHZ) RM0453 5.10.37 Sub-GHz radio bandwidth select register (SUBGHZ_BWSELR) Address offset: 0x807 Reset value: 0x00 CHBWMANT[1:0] CHBWEXPO[2:0] Bits 7:5 Reserved, must be kept at reset value. Bits 4:3 CHBWMANT[1:0]: Channel bandwidth mantissa Bits 2:0 CHBWEXP[2:0]: Channel bandwidth exponent 5.10.38 Sub-GHz radio random number register 3 (SUBGHZ_RNGR3) Address offset: 0x819... -
Page 219: Sub-Ghz Radio Random Number Register 0 (Subghz_Rngr0)
RM0453 Sub-GHz radio (SUBGHZ) 5.10.41 Sub-GHz radio random number register 0 (SUBGHZ_RNGR0) Address offset: 0x81C Reset value: 0x00 RNDATA[7:0] Bits 7:0 RNDATA[7:0]: Random number data bits [7:0] 5.10.42 Sub-GHz radio SD resolution register (SUBGHZ_SDCFG0R) Address offset: 0x889 Reset value: 0x00 SD[7:0] Bits 7:0 SD[7:0]: Radio SD resolution 5.10.43... -
Page 220: Sub-Ghz Radio Agc Reset Configuration Register
Sub-GHz radio (SUBGHZ) RM0453 Bits 1:0 PMODE[1:0]: Receiver power mode selection between normal mode and power saving mode 00: power saving mode (reduced sensitivity) 01: boost mode level1 active (improves sensitivity at detriment of power consumption) 10: boost mode level2 active (improves a set further sensitivity at detriment of power consumption) Others: boost mode (best receiver sensitivity) 5.10.45... -
Page 221: Sub-Ghz Radio Disable Lna Register (Reg_Ana_Lna)
RM0453 Sub-GHz radio (SUBGHZ) 5.10.48 Sub-GHz radio disable LNA register (REG_ANA_LNA) Address offset: 0x8E2 Reset value: 0x00 Bits 7:0 Reserved, must be kept at reset value. 5.10.49 Sub-GHz radio disable mixer register (REG_ANA_MIXER) Address offset: 0x8E5 Reset value: 0x00 Bits 7:0 Reserved, must be kept at reset value. 5.10.50 Sub-GHz radio PA over current protection register (SUBGHZ_PAOCPR) -
Page 222: Sub-Ghz Radio Rtc Period Msb Register (Subghz_Rtcprdr2)
Sub-GHz radio (SUBGHZ) RM0453 Bits 7:1 Reserved, must be kept at reset value. Bit 0 RTCEN: Writing 1 restarts the radio RTC. 5.10.52 Sub-GHz radio RTC period MSB register (SUBGHZ_RTCPRDR2) Address offset: 0x906 Reset value: 0x00 RTCPRD[31:16] Bits 7:0 RTCPRD[31:16]: Updates radio RTC period (MSB) 5.10.53 Sub-GHz radio RTC period mid-byte register (SUBGHZ_RTCPRDR1) -
Page 223: Sub-Ghz Radio Hse32 Osc_In Capacitor Trim Register
RM0453 Sub-GHz radio (SUBGHZ) 5.10.55 Sub-GHz radio HSE32 OSC_IN capacitor trim register (SUBGHZ_HSEINTRIMR) Address offset: 0x911 Reset value: 0x12 This register is retained in Sleep mode, but lost in Deep-Sleep mode. Res. Res. TRIM[5:0] Bits 7:6 Reserved, must be kept at reset value. Bits 5:0 TRIM[5:0]: HSE32 XTAL mode OSC_IN load capacitor trimming Load capacitor trimming step size ~0.47 pf. -
Page 224: Sub-Ghz Radio Smps Control 0 Register (Subghz_Smpsc0R)
Sub-GHz radio (SUBGHZ) RM0453 5.10.57 Sub-GHz radio SMPS control 0 register (SUBGHZ_SMPSC0R) Address offset: 0x916 Reset value: 0x00 Res. CLKDE Res. Res. Res. Res. Res. Res. Bit 7 Reserved, must be kept at reset value. Bit 6 CLKDE: SMPS clock detection enable SMPS clock detection must be enabled before enabling the SMPS, if the application uses an external HSE clock source (not coming from XO or TCXO but from another device). -
Page 225: Sub-Ghz Radio Regulator Drive Control Register
RM0453 Sub-GHz radio (SUBGHZ) 5.10.59 Sub-GHz radio regulator drive control register (SUBGHZ_REGDRVCR) Address offset: 0x91F Reset value: 0x08 This register is retained in Sleep mode but lost in Deep-Sleep mode. TRIM[2:0 Bits 7:4 Reserved, must be kept at reset value. Bits 3:1 TRIM[2:0]: Regulator drive trimming 000: 1.22 001: 1.24... -
Page 226: Sub-Ghz Radio Register Map
Sub-GHz radio (SUBGHZ) RM0453 5.10.61 Sub-GHz radio register map Table 42. SUBGHZ register map and reset values Offset Register name SUBGHZ_GBSYNCR Res. RXDINV Res. Res. Res. Res. 0x6AC Reset value 0x6AC- Reserved Reserved 0x6B4 SUBGHZ_GPKTCTL1AR Res. Res. CONTTX INFSQEQSEL[1:0] 0x6B8 Reset value SUBGHZ_GWHITEINIRL WHITEINI[7:0]... - Page 227 RM0453 Sub-GHz radio (SUBGHZ) Table 42. SUBGHZ register map and reset values (continued) Offset Register name SUBGHZ_RNGR3 RNDATA[31:24] 0x819 Reset value SUBGHZ_RNGR2 RNDATA[23:16] 0x81A Reset value SUBGHZ_RNGR1 RNDATA[15:8] 0x81B Reset value SUBGHZ_RNGR0 RNDATA[7:0] 0x81C Reset value SUBGHZ_AGCRSSIC0R Res. MODE LENGTH[2:0] Res.
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Page 228: Power Control (Pwr)
Power control (PWR) RM0453 Power control (PWR) Power supplies The STM32WL5x devices require a V operating voltage supply between 1.71 V and 3.6 V. Several independent supplies (V ) can be provided for DDSMPS FBSMPS DDRF specific peripherals: • = 1.71 V to 3.6 V is the external power supply for the I/Os, the system analog blocks such as reset, power management, internal clocks and low-power regulator. -
Page 229: Figure 18. Power Supply Overview
RM0453 Power control (PWR) VREF+ pin is not available on all packages. When not available, this pin is internally bonded to VDDA. When VREF+ is double-bonded with VDDA in a package, the internal voltage reference buffer is not available and must be kept disabled (refer to the datasheet for pinout descriptions). -
Page 230: Figure 19. Supply Configurations
Power control (PWR) RM0453 The different supply configurations are shown in the figure below. Figure 19. Supply configurations DDSMPS DDSMPS LDO/SMPS LDO/SMPS LXSMPS LXSMPS FBSMPS FBSMPS DDRF1V5 DDRF1V5 LDO/SMPS supply LDO supply MSv50974V1 The LDO or SMPS step-down converter operating mode can be configured by one of the following: •... -
Page 231: Independent Analog Peripherals Supply
RM0453 Power control (PWR) The inrush current of the LDO and SMPS step-down converter can be controlled via the sub- GHz radio SUBGHZ_PCR register. This information is retained in all but the sub-GHz radio Deep-Sleep mode. For more details see Section 5: Sub-GHz radio (SUBGHZ). - Page 232 Power control (PWR) RM0453 The VBAT pin powers RTC, TAMP, the LSE oscillator and the PC13 to PC15 I/Os, allowing RTC and TAMP to operate even when the main power supply is turned off. The switch to the supply is controlled by the power-down reset embedded in the reset block. Warning: During (temporization at V...
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Page 233: Voltage Regulator
RM0453 Power control (PWR) VBAT battery charging When V is present, It is possible to charge the external battery on VBAT through an internal resistance. The VBAT charging is done either through a 5 kΩ resistor or through a 1.5 kΩ resistor, depending on the VBRS bit value in the PWR control register 4 (PWR_CR4). -
Page 234: Power Supply Supervisor
Power control (PWR) RM0453 Dynamic voltage scaling to decrease V is known as “undervolting”. It is used to save CORE power, particularly in laptop and other mobile devices where the energy comes from a battery and is thus limited. • range 1: high-performance range The main regulator provides a typical output voltage at 1.2 V. -
Page 235: Programmable Voltage Detector (Pvd)
RM0453 Power control (PWR) Figure 20. Brownout reset waveform BORH rise hysteresis BORH fall nPwr MS44480V1 1. The reset temporization t is present only for the BOR lowest threshold (V RSTTEMPO BOR0 6.2.2 Programmable voltage detector (PVD) The PVD can be used to monitor V by comparing it to a threshold selected by the PLS[2:0] bits in the PWR control register 2... -
Page 236: Peripheral Voltage Monitoring (Pvm)
Power control (PWR) RM0453 Figure 21. PVD thresholds , or PVD_IN rise hysteresis fall PVDO PVDE SW enable PDR reset MS44481V1 6.2.3 Peripheral voltage monitoring (PVM) Only V is monitored by default as it is the only supply required for all system-related functions. -
Page 237: Radio End Of Life (Eol)
RM0453 Power control (PWR) The independent supply V is not considered as present by default and a logical and electrical isolation is applied to ignore any information coming from the peripherals supplied by these dedicated supplies: • If V is shorted externally to V , the application must assume that V is available without enabling any peripheral voltage monitoring. -
Page 238: Figure 23. Radio Busy Management
Power control (PWR) RM0453 the SUBGHZSPI_NSS activity, and masks the RFBUSYS status low time (not busy) after an SPI command transfer (see the figure below). Figure 23. Radio busy management SUBGHZSPI_DATA SUBGHZSPI_NSS RFBUSY/RFBUSYS RFBUSYMS minimum RFBUSYSM delay EXTI RFBUSY interrupt (Stop, Run) WRFBUSYF wakeup (from Standby) MSv50975V1 At reset, the radio is busy (as signaled by the RFBUSY signal). -
Page 239: Cpu2 Boot
RM0453 Power control (PWR) CPU2 boot The CPU2 boot is controlled by the following sources: • from C2BOOT bit in PWR control register 4 (PWR_CR4) This allows the CPU1 to initialize the system after a reset or wake-up from system Low- power mode, before booting the CPU2. -
Page 240: Figure 24. Cpu2 Boot Options
Power control (PWR) RM0453 Figure 24. CPU2 boot options ILAC handling LP-RUN CPU2 CSTOP CPU1 CRUN, CSLEEP, CPU2 CRUN, CSLEEP Reset C2BOOTS = 0 (ILAC) CPU1 CRUN, CSLEEP, CPU1 CRUN or CSLEEP CPU2 CSTOP (BOOT HOLD) CPU2 CRUN or CSLEEP C2BOOT = 1 (C2BOOTS = 1) CPU1 CRUN or CSLEEP... -
Page 241: Low-Power Modes
RM0453 Power control (PWR) When CPU2 is prevented from booting (C2BOOT = 0, boot hold), the wake-up from low-power mode boot procedure is the following: • When the system is secure (ESE = 1) and the secure CPU2 boots after reset (POR/NRST or wake-up from Standby), CPU2 checks the reset source (C2BOOT or illegal access) in the C2BOOTS bit, as follows: –... - Page 242 Power control (PWR) RM0453 radio may remain active independently from the CPUs. Some peripherals with the wake-up capability can enable HSI16 RC during the Stop mode to detect their wake-up condition. Stop 1 offers the largest number of active peripherals and wake-up sources, a smaller wake-up time but a higher consumption compared with Stop 2.
- Page 243 RM0453 Power control (PWR) The system operation mode depends on the CPU1 and the CPU2 sub-system operating mode. The system only enters a low-power mode when both sub-systems allow it to do so. After a system reset, CPU1 is in CRUN mode. CPU2 only boots if enabled by CPU1 via the C2BOOT bit, or when the system is secure on an illegal access detection.
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Page 244: Figure 25. Cpus Low-Power Modes Possible Transitions
Power control (PWR) RM0453 Figure 25. CPUs low-power modes possible transitions Sub-system modes Bus modes System modes LP-RUN Wakeup from STOP with CPU HOLD CPU2 sub-system having allocated peripheral in the HCLK1 domain CPU1 CRUN or CSLEEP CPU1 CSTOP C1_wakeup C1STOP CPU2 CRUN or CSLEEP CPU2 CRUN or CSLEEP... -
Page 245: Table 44. Low-Power Mode Summary
RM0453 Power control (PWR) Table 44. Low-power mode summary Voltage Wake-up Wake-up regulators Mode name Entry Effect on clocks source system clock WFI or return CPU clock OFF Sleep Any interrupt Same as before from ISR (Sleep-now or No effect on other clocks entering Sleep mode Sleep-on-exit) or analog clock sources... -
Page 246: Table 45. Functionalities Depending On System Operating Mode
Power control (PWR) RM0453 Table 45. Functionalities depending on system operating mode Stop 0 Stop 1 Stop 2 Standby Shutdo Peripheral CPU1 CPU2 Radio-system (sub-GHz) Flash memory (up to 256 Kbytes) Flash memory interface SRAM1 SRAM2 Backup registers Brownout reset (BOR) Programmable voltage detector (PVD) Peripheral voltage monitor... - Page 247 RM0453 Power control (PWR) Table 45. Functionalities depending on system operating mode (continued) Stop 0 Stop 1 Stop 2 Standby Shutdo Peripheral SUBGHZSPI SPI2S2 VREFBUF COMPx (x = 1, 2) Temperature sensor Timers (TIMx) x = 1, 2, 16, 17) LPTIM1 LPTIMx (x = 2, 3) Independent watchdog...
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Page 248: Table 46. Mcu And Sub-Ghz Radio Operating Modes
Power control (PWR) RM0453 4. The SRAM2 content can optionally be retained when the PWR_CR3.RRS bit is set. 5. Only when the sub-GHz radio is active. 6. Some peripherals with wake-up from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral that requested it. -
Page 249: Run Mode
RM0453 Power control (PWR) Debug mode By default, the debug connection is lost if the application puts the MCU in Stop 0, Stop 1, Stop 2, Standby or Shutdown mode while the debug features are used. This is because the CPU core is no longer clocked. -
Page 250: Enter Low-Power Mode
Power control (PWR) RM0453 Refer to the product datasheet for more details on voltage regulator and peripherals operating conditions. I/O states in LPRun mode In LPRun mode, all I/O pins keep the same state as in Run mode. Enter LPRun mode To enter the LPRun mode, proceed as follows (refer to Table 47):... - Page 251 RM0453 Power control (PWR) mode was entered, as detailed below: • If the WFI instruction or return from ISR was used to enter the low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device. • If the WFE instruction is used to enter the low-power mode, the CPU exits the low-power mode as soon as an event occurs.
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Page 252: Sleep Mode
Power control (PWR) RM0453 Table 48. CPU wake-up versus system operating mode CPU1 CPU2 System CPU1 wake-up CPU2 wake-up mode Wake-up from Run Wake-up from Run Wake-up from Stop, but system is Wake-up from Run already in Run due to CPU2 Wake-up from Stop, but system is Wake-up from Run already in Run due to CPU1... -
Page 253: Low-Power Sleep Mode (Lpsleep)
RM0453 Power control (PWR) Table 49. Sleep mode Sleep mode Description WFI (wait for interrupt) or WFE (wait for event) while: – SLEEPDEEP = 0 – No interrupt (for WFI) or event (for WFE) is pending Refer to the Cortex system control register. Mode entry On return from ISR while: –... -
Page 254: Stop 0 Mode
Power control (PWR) RM0453 The table below details how to exit the LPSleep mode. Table 50. LPSleep LPSleep mode Description LPSleep mode is entered from the LPRun mode. WFI (wait for interrupt) or WFE (wait for event) while: – SLEEPDEEP = 0 –... - Page 255 RM0453 Power control (PWR) Enter Stop 0 mode The Stop 0 mode is entered according Section 6.5.3, when the SLEEPDEEP bit in the Cortex system control register is set (see Table 51). If flash memory programming is ongoing, the Stop 0 mode entry is delayed until the operation is completed.
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Page 256: Stop 1 Mode
Power control (PWR) RM0453 When exiting the Stop 0 mode, the MCU is either in Run mode (range 1 or range 2 depending on VOS bit in PWR control register 1 (PWR_CR1)) or in LPRun mode if the bit LPR is set in the same register. Table 51. -
Page 257: Stop 2 Mode
RM0453 Power control (PWR) REGLPS bit can be used to check that the low-power regulator is ready (see the table below). Table 52. Stop 1 mode Stop 1 Description WFI (wait for interrupt) or WFE (wait for event) while: – SLEEPDEEP bit is set in Cortex system control register –... - Page 258 Power control (PWR) RM0453 SRAM1, SRAM2, PWR, flash memory interface, RCC, GTZC TZSC, GTZC TZIC, EXTI, IPCC, IWDG, WWDG, GPIO, CRC, SYSCFG, RTC and TAMP contents and registers in the backup domain are also preserved. The content of all other peripherals is reset and must be reprogrammed.
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Page 259: Standby Mode
RM0453 Power control (PWR) exiting the Stop 2 mode, the MCU is in Run mode (range 1 or range 2 depending on VOS bit in PWR_CR1). Table 53. Stop 2 mode Stop 2 Description WFI (wait for interrupt) or WFE (wait for event) while: –... - Page 260 Power control (PWR) RM0453 I/O states in Standby mode In Standby mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx registers (x = A, B, C, H)), or with a pull-down (refer to PWR_PDCRx registers (x = A, B, C, H)), or can be kept in analog state.
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Page 261: Shutdown Mode
RM0453 Power control (PWR) Refer to the table below for more details on how to exit Standby mode. Table 54. Standby mode Standby Description WFI (wait for interrupt) or WFE (wait for event) while: – SLEEPDEEP bit is set in Cortex system control register –... -
Page 262: Auto-Wake-Up From Low-Power Mode
Power control (PWR) RM0453 In Shutdown mode, the following features can be selected by programming individual control bits: • Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain control register (RCC_BDCR). Caution: In case of V power-down, the RTC content is lost. -
Page 263: Pwr Registers
RM0453 Power control (PWR) following alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the RCC backup domain control register (RCC_BDCR): • Low-power 32.768 kHz external crystal oscillator (LSE OSC) This clock source provides a precise time base with very low-power consumption. •... - Page 264 Power control (PWR) RM0453 Bits 31:15 Reserved, must be kept at reset value. Bit 14 LPR: LPRun When this bit is set, the supply mode is switched from main regulator mode (MR) to low- power regulator mode (LPR). Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead. Bits 13:11 Reserved, must be kept at reset value.
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Page 265: Pwr Control Register 2 (Pwr_Cr2)
RM0453 Power control (PWR) Bit 4 FPDR: Flash memory power-down mode during LPRun for CPU1 This bit can only be written to 1 after unlocking this register bit, by first writing (code 0xC1B0) into this register (when writing the code, the register bits are not updated). Selects whether the flash memory is in power-down mode or Idle mode when in LPRun mode. -
Page 266: Pwr Control Register 3 (Pwr_Cr3)
Power control (PWR) RM0453 Bits 3:1 PLS[2:0]: Programmable voltage detector level selection. These bits select the voltage threshold detected by the programmable voltage detector: 000: V around 2.0 V PVD0 001: V around 2.2 V PVD1 010: V around 2.4 V PVD2 011: V around 2.5 V... - Page 267 RM0453 Power control (PWR) Bit 13 EWRFIRQ: radio IRQ[2:0] wake-up for CPU1 enable When this bit is set, the radio IRQ[2:0] is enabled and triggers a wake-up from Standby event to CPU1. Bit 12 Reserved, must be kept at reset value. Bit 11 EWRFBUSY: radio busy wake-up from Standby for CPU1 enable When this bit is set, the radio busy is enabled and triggers a wake-up from Standby event to CPU1 when a rising or a falling edge occurs.
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Page 268: Pwr Control Register 4 (Pwr_Cr4)
Power control (PWR) RM0453 Bit 2 EWUP3: Wake-up pin WKUP3 for CPU1 enable When this bit is set, the external wake-up pin WKUP3 is enabled and triggers an interrupt and wake-up from Stop, Standby or Shutdown event when a rising or a falling edge occurs to CPU1. -
Page 269: Pwr Status Register 1 (Pwr_Sr1)
RM0453 Power control (PWR) Bit 9 VBRS: V battery charging resistor selection 0: V charging through a 5 kΩ resistor 1: V charging through a 1.5 kΩ resistor Bit 8 VBE: V battery charging enable 0: V battery charging disabled 1: V battery charging enabled Bits 7:3 Reserved, must be kept at reset value. -
Page 270: Power Status Register 2 (Pwr_Sr2)
Power control (PWR) RM0453 Bit 11 WRFBUSYF: Radio busy wake-up flag This bit is set when a wake-up event is detected on radio busy. It is cleared by writing ‘1’ in the CWRFBUSYF bit of the PWR_SCR register. Bits 10:9 Reserved, must be kept at reset value. Bit 8 WPVDF: Wake-up PVD flag This bit is set when a wake-up event is detected on PVD. - Page 271 RM0453 Power control (PWR) Bit 10 VOSF: Voltage scaling flag A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR control register 1 (PWR_CR1).
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Page 272: Pwr Status Clear Register (Pwr_Scr)
Power control (PWR) RM0453 Bit 2 RFBUSYMS: Radio busy masked signal status This bit indicates the actual status of the radio busy masked signal. 0: radio busy masked signal low (not busy) 1: radio busy masked signal high (busy) Bit 1 RFBUSYS: Radio busy signal status This bit indicates the actual status of the radio busy signal. -
Page 273: Pwr Control Register 5 (Pwr_Cr5)
RM0453 Power control (PWR) Bit 2 CWUF3: Clear wake-up flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register. This bit is always read as 0. Bit 1 CWUF2: Clear wake-up flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register. This bit is always read as 0. Bit 0 CWUF1: Clear wake-up flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register. -
Page 274: Pwr Port A Pull-Up Control Register (Pwr_Pucra)
Power control (PWR) RM0453 6.6.9 PWR port A pull-up control register (PWR_PUCRA) This register is not reset when exiting Standby modes. Access: additional APB cycles are needed to access this register versus those needed for a standard APB access (three for a write and two for a read). Address offset: 0x020 Reset value: 0x0000 0000 Res. -
Page 275: Pwr Port B Pull-Up Control Register (Pwr_Pucrb)
RM0453 Power control (PWR) 6.6.11 PWR port B pull-up control register (PWR_PUCRB) This register is not reset when exiting Standby modes. Access: additional APB cycles are needed to access this register versus those needed for a standard APB access (three for a write and two for a read). Address offset: 0x028 Reset value: 0x0000 0000 Res. -
Page 276: Pwr Port C Pull-Up Control Register (Pwr_Pucrc)
Power control (PWR) RM0453 6.6.13 PWR port C pull-up control register (PWR_PUCRC) This register is not reset when exiting Standby modes. Access: additional APB cycles are needed to access this register versus those needed for a standard APB access (three for a write and two for a read). Address offset: 0x030 Reset value: 0x0000 0000 Res. -
Page 277: Pwr Port H Pull-Up Control Register (Pwr_Pucrh)
RM0453 Power control (PWR) Bits 15:13 PD[15:13]: Port PC[y] pull-down (y = 13 to 15) When set, each bit activates the pull-down on PC[y] when both APC bits are set in control register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3). -
Page 278: Pwr Cpu2 Control Register 1 (Pwr_C2Cr1)
Power control (PWR) RM0453 Bits 31:4 Reserved, must be kept at reset value. Bit 3 PD3: Port PH[3] pull-down When set, this bit activates the pull-down on PH[3] when both APC bits are set in control register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3). -
Page 279: Pwr Cpu2 Control Register 3 (Pwr_C2Cr3)
RM0453 Power control (PWR) Bit 3 Reserved, must be kept at reset value. Bits 2:0 LPMS[2:0]: Low-power mode selection for CPU2 These bits are not reset when exiting Standby mode. These bits select the low-power mode entered when CPU2 enters the Deep-Sleep mode. The system low-power mode entered depends also on the PWR_CR1.LPMS[2:0] allowed Low-power mode from CPU1. -
Page 280: Pwr Extended Status And Status Clear Register (Pwr_Extscr)
Power control (PWR) RM0453 Bit 10 APC: Apply pull-up and pull-down configuration for CPU2 When this bit for CPU2, and the PWR_CR3.APC bit for CPU1, are set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. - Page 281 RM0453 Power control (PWR) Bit 15 C2DS: CPU2 Deep-Sleep mode This bit is set by hardware when CPU2 enters Deep-Sleep mode or is hold by C2BOOT. 0: CPU2 running or in sleep 1: CPU2 in Deep-Sleep or hold by C2BOOT Bit 14 C1DS: CPU1 Deep-Sleep mode This bit is set by hardware when CPU1 enters Deep-Sleep mode.
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Page 282: Pwr Security Configuration Register (Pwr_Seccfgr)
Power control (PWR) RM0453 6.6.20 PWR security configuration register (PWR_SECCFGR) Address offset: 0x08C Reset value: 0x0000 8000 This register is not reset when exiting Standby modes. Access: three additional APB cycles are needed to write this register versus a standard APB write. -
Page 283: Pwr Rss Command Register (Pwr_Rsscmdr)
RM0453 Power control (PWR) Bits 14:0 Reserved, must be kept at reset value. 6.6.22 PWR RSS command register (PWR_RSSCMDR) This register is only reset by a power-on reset (not reset on NRST and exit from Standby). Address offset: 0x098 Reset value: 0x0000 0000 Res. - Page 284 Power control (PWR) RM0453 Table 56. PWR register map and reset values (continued) Offset Register name PWR_SR2 0x014 Reset value PWR_SCR 0x018 Reset value PWR_CR5 0x01C Reset value PWR_PUCRA 0x020 Reset value PWR_PDCRA 0x024 Reset value PWR_PUCRB 0x028 Reset value PWR_PDCRB 0x02C Reset value...
- Page 285 RM0453 Power control (PWR) Table 56. PWR register map and reset values (continued) Offset Register name PWR_SECCFGR 0x08C Reset value PWR_ SUBGHZSPICR 0x090 Reset value PWR_RSSCMDR RSSCMD[7:0] 0x098 Reset value Refer to Section 2.6 for the register boundary addresses. RM0453 Rev 5 285/1450...
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Page 286: Reset And Clock Control (Rcc)
Reset and clock control (RCC) RM0453 Reset and clock control (RCC) Reset There are three types of reset, defined as system reset, power reset and backup domain reset. 7.1.1 Power reset A power reset is generated when one of the following events occurs: •... -
Page 287: Figure 26. Simplified Diagram Of The Reset Circuit
RM0453 Reset and clock control (RCC) In case on an internal reset, the internal pull-up R is deactivated in order to save the power consumption through the pull-up resistor. Figure 26. Simplified diagram of the reset circuit System reset External Filter reset NRST... -
Page 288: Backup Domain Reset
Reset and clock control (RCC) RM0453 7.1.3 Backup domain reset The backup domain has two specific resets. A backup domain reset is generated when one of the following events occurs: • a software reset, triggered by setting the BDRST bit in the RCC backup domain control register (RCC_BDCR) •... - Page 289 RM0453 Reset and clock control (RCC) Most peripheral clocks are derived from their bus clock (HCLK, PCLK) except the following: • The clock used for true RNG, is derived (selected by software) from one of the following sources: – PLL VCO (PLLQCLK) (only available in Run mode) –...
- Page 290 Reset and clock control (RCC) RM0453 • The RTC clock is derived (selected by software) from one of the following sources: – LSE clock – LSI clock – HSE32 clock divided by 32 The functionality in Stop mode (including wake-up) is supported only when the clock is LSI or LSE.
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Page 291: Hse32 Clock With Trimming
RM0453 Reset and clock control (RCC) Figure 27. Clock tree LSIPRE to IWDG LSI RCC 32 kHz /1,128 LSCO LSE OSC OSC32_OUT 32.768 kHz to RTC OSC32_IN LSE CSS CPU1 HCLK1 to CPU1, AHB1, AHB2 HPRE /1,2,...,512 HSE32 to CPU1 FCLK SYSCLK to CPU1 system timer PLLRCLK... -
Page 292: Figure 28. Hse32 Clock Sources
Reset and clock control (RCC) RM0453 HSE32 is controlled from the CPUs and from the sub-GHz radio (see Section 5: Sub-GHz radio (SUBGHZ)). HSE32 can be switched on and off using the HSEON bit in the RCC clock control register (RCC_CR). -
Page 293: Figure 29. Hse32 Tcxo Control
RM0453 Reset and clock control (RCC) Frequency trimming When using HSE32 with external crystal, the load capacitors are provided by the integrated capacitor banks, that can be trimmed. The HSE32 load capacitor trimming allows a compensation of device manufacturing process variations, used crystal and PCB design. The HSE32 frequency can be tuned in the application via the sub-GHz radio registers SUBGHZ_HSEINTRIMR and SUBGHZ_HSEOUTRIMR. -
Page 294: Hsi16 Clock
Reset and clock control (RCC) RM0453 When the CPUs are in one of the low-power modes (Stop, Standby, or Shutdown) and the sub-GHz radio is in Sleep, the HSE32 clock including the TCXO is disabled. 7.2.2 HSI16 clock The HSI16 clock signal is generated from an internal 16 MHz Oscillator. The HSI16 oscillator has the advantage of providing a clock source at low cost. -
Page 295: Pll
RM0453 Reset and clock control (RCC) The MSI clock can be selected as system clock after a wake-up from Stop mode (Stop 0, Stop 1 or Stop 2, see Section 7.3: Low-power modes). It can also be used as a backup clock source (auxiliary clock for the CPUs) if the HSE32 crystal oscillator fails (see Section 7.2.10: Clock security system on HSE32... -
Page 296: Lse Clock
Reset and clock control (RCC) RM0453 The PLLQCLK and PLLRCLK output frequency must not exceed 48 MHz. The PLLPCLK output frequency must not exceed 62 MHz. The enable bits of the PLL output clock (PLLPEN, PLLQEN, PLLREN) can be modified at any time without stopping the PLL. -
Page 297: Lsi Clock
RM0453 Reset and clock control (RCC) External source (LSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the RCC backup domain control register (RCC_BDCR). -
Page 298: Clock Source Frequency Versus Voltage Scaling
Reset and clock control (RCC) RM0453 A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source that is not yet ready is selected, the switch occurs when the clock source becomes ready. -
Page 299: Clock Security System On Lse (Lsecss)
RM0453 Reset and clock control (RCC) 7.2.11 Clock security system on LSE (LSECSS) A CSS on LSE can be activated by software writing the LSECSSON bit in the RCC backup domain control register (RCC_BDCR). This bit can be disabled only by a hardware reset or RTC software reset, or after a failure detection on LSE. -
Page 300: Adc Clock
Reset and clock control (RCC) RM0453 Table 60. Sub-GHz radio SPI clock configurations PCLK3 [MHz] SUBGHZSPI_SCK clock maximum speed PCLK / 4 = 12 MHz PCLK / 2 = 16 MHz 1. As controlled by SUBGHZSPI_CR1 BR baud rate control. 7.2.14 ADC clock The ADC clock is derived from the system clock, from the HSI16 clock, or from the PLL... -
Page 301: Watchdog Clock
RM0453 Reset and clock control (RCC) 7.2.17 Watchdog clock If the independent watchdog (IWDG) is started by an hardware option or a software access, the LSI clock is forced on. If the LSI oscillator is disabled when starting the IWDG, the LSI oscillator is forced on. After the LSI oscillator temporization, the clock is provided to the IWDG. -
Page 302: Internal/External Clock Measurement With Tim16/Tim17
Reset and clock control (RCC) RM0453 7.2.20 Internal/external clock measurement with TIM16/TIM17 The frequency of all on-board clock sources can be indirectly measured by mean of the TIM16 or TIM17 channel 1 input capture, as shown in Figure 31 Figure Figure 31. - Page 303 RM0453 Reset and clock control (RCC) The TIM17 input capture channel can be a GPIO line or an internal clock of the MCU. This selection is performed through the TI1_RMP[1:0] bits in the TIM17_OR register. The possibilities are listed below: •...
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Page 304: Table 61. Peripheral Clock Enable
Reset and clock control (RCC) RM0453 7.2.21 Peripheral clocks enable Most peripheral bus and kernel clocks can be individually enabled per CPU.The RCC_AHBxENR and RCC_APBxENRy registers enable peripheral clocks for CPU1. RCC_C2_AHBxENR and RCC_C2_APBxENR registers enable peripheral clocks for CPU2. The peripheral clocks follow the CPUs state for which it is enabled and the system state (see the table below). -
Page 305: Table 62. Low-Power Debug Configurations
RM0453 Reset and clock control (RCC) Low-power modes AHB and APB peripheral clocks, including DMA clock, can be disabled by software. Sleep and LPSleep modes stop the CPU clock. The memory interface clocks (flash memory and SRAM1/2 interfaces) can be stopped during Sleep mode by software using the SRAMxSMEN bits. - Page 306 Reset and clock control (RCC) RM0453 Table 62. Low-power debug configurations (continued) CDBGPW DBGMCU Debug RUPREQ Mode DBG_ DBG_ CPU1 CPU2 DBG_STOP CPU1 CPU2 STANDBY SLEEP Disabled Disabled Disabled Disable Standby Enabled Enabled Enabled Enabled 1. x = Don’t care. 2.
- Page 307 RM0453 Reset and clock control (RCC) RCC registers 7.4.1 RCC clock control register (RCC_CR) Address offset: 0x000 Reset value: 0x0000 0061 Access: no wait state, word, half-word and byte access HSEBY Res. Res. Res. Res. Res. Res. PLLON Res. Res. Res.
- Page 308 Reset and clock control (RCC) RM0453 Bit 17 HSERDY: HSE32 clock ready flag This bit is set and cleared by hardware to indicate that the HSE32 oscillator is stable or not. 0: HSE32 oscillator not ready 1: HSE32 oscillator ready Note: Once HSEON is cleared, HSERDY goes low after six HSE32 clock cycles.
- Page 309 RM0453 Reset and clock control (RCC) Bit 8 HSION: HSI16 clock enable This bit is set and cleared by software. It is also cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode. This bit is set by hardware to force the HSI16 oscillator on when STOPWUCK = 1 or HSIASFS = 1 when exiting Stop modes, or in case of HSE32 crystal oscillator failure.
- Page 310 Reset and clock control (RCC) RM0453 Bit 0 MSION: MSI clock enable This bit is set and cleared by software. It is also cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode. This bit is set by hardware to force the MSI oscillator on when exiting Standby or Shutdown mode.
- Page 311 RM0453 Reset and clock control (RCC) 7.4.3 RCC clock configuration register (RCC_CFGR) Address offset: 0x008 Reset value: 0x0007 0000 (after POR reset and after wake-up from Standby) Access: 0 ≤ wait state ≤ 2, word, half-word and byte access One or two wait states inserted only if the access occurs during clock source switch. From 0 to 15 wait states inserted if the access occurs when the APB or AHB prescalers values update is ongoing.
- Page 312 Reset and clock control (RCC) RM0453 Bit 18 PPRE2F: PCLK2 prescaler flag (APB2) This bit is set and reset by hardware to acknowledge PCLK2 prescaler programming. It is reset when a new prescaler value is programmed in PPRE2 and set when the programmed value is actually applied.
- Page 313 RM0453 Reset and clock control (RCC) Bits 7:4 HPRE[3:0]: HCLK1 prescaler (CPU1, AHB1, and AHB2.) These bits are set and cleared by software to control the division factor of the HCLK1 clock (CPU1, AHB1, AHB2). The HPREF flag can be checked to know if the programmed HPRE prescaler value is applied.
- Page 314 Reset and clock control (RCC) RM0453 7.4.4 RCC PLL configuration register (RCC_PLLCFGR) Address offset: 0x00C Reset value: 0x2204 0100 Access: no wait state, word, half-word and byte access This register is used to configure the main PLL clock outputs according to the formulas: •...
- Page 315 RM0453 Reset and clock control (RCC) Bits 27:25 PLLQ[2:0]: Main PLL division factor for PLLQCLK These bits are set and cleared by software to control the frequency of the main PLL output clock PLLQCLK. This output can be selected for True RNG clock. These bits can be written only if PLL is disabled.
- Page 316 Reset and clock control (RCC) RM0453 Bits 14:8 PLLN[6:0]: Main PLL multiplication factor for VCO These bits are set and cleared by software to control the multiplication factor of the VCO. They can be written only when the PLL is disabled. VCO output frequency = VCO input frequency x PLLN with 6<...
- Page 317 RM0453 Reset and clock control (RCC) 7.4.5 RCC clock interrupt enable register (RCC_CIER) Address offset: 0x018 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 318 Reset and clock control (RCC) RM0453 Bit 2 MSIRDYIE: MSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization. 0: MSI ready interrupt disabled 1: MSI ready interrupt enabled Bit 1 LSERDYIE: LSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.
- Page 319 RM0453 Reset and clock control (RCC) Bit 4 HSERDYF: HSE32 ready interrupt flag This bit is set by hardware when the HSE32 clock becomes stable and HSERDYDIE is set. It is cleared by software setting the HSERDYC bit. 0: No clock ready interrupt caused by the HSE32 oscillator 1: Clock ready interrupt caused by the HSE32 oscillator Bit 3 HSIRDYF: HSI16 ready interrupt flag This bit is set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in...
- Page 320 Reset and clock control (RCC) RM0453 Bits 31:10 Reserved, must be kept at reset value. Bit 9 LSECSSC: LSE CSS flag clear This bit is set by software to clear the LSECSSF flag. 0: No effect 1: LSECSSF flag cleared Bit 8 CSSC: HSE32 CSS flag clear This bit is set by software to clear the HSE32 CSSF flag.
- Page 321 RM0453 Reset and clock control (RCC) 7.4.8 RCC AHB1 peripheral reset register (RCC_AHB1RSTR) Address offset: 0x028 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 322 Reset and clock control (RCC) RM0453 Bits 31:8 Reserved, must be kept at reset value. Bit 7 GPIOHRST: IO port H reset This bit is set and cleared by software. 0: No effect 1: IO port H reset Bits 6:3 Reserved, must be kept at reset value. Bit 2 GPIOCRST: IO port C reset This bit is set and cleared by software.
- Page 323 RM0453 Reset and clock control (RCC) Bit 19 HSEMRST: HSEM reset This bit is set and cleared by software. 0: No effect 1: HSEM reset Bit 18 RNGRST: True RNG reset This bit is set and cleared by software. 0: No effect 1: True RNG reset Bit 17 AESRST: AES hardware accelerator reset This bit is set and cleared by software.
- Page 324 Reset and clock control (RCC) RM0453 Bit 23 I2C3RST: I2C3 reset This bit is set and cleared by software. 0: No effect 1: I2C3 reset Bit 22 I2C2RST: I2C2 reset This bit is set and cleared by software. 0: No effect 1: I2C2 reset Bit 21 I2C1RST: I2C1 reset This bit is set and cleared by software.
- Page 325 RM0453 Reset and clock control (RCC) Bits 31:7 Reserved, must be kept at reset value. Bit 6 LPTIM3RST: Low-power timer 3 reset This bit is set and cleared by software. 0: No effect 1: LPTIM3 reset Bit 5 LPTIM2RST: Low-power timer 2 reset This bit is set and cleared by software.
- Page 326 Reset and clock control (RCC) RM0453 Bit 12 SPI1RST: SPI1 reset This bit is set and cleared by software. 0: No effect 1: SPI1 reset Bit 11 TIM1RST: Timer 1 reset This bit is set and cleared by software. 0: No effect 1: TIM1 reset Bit 10 Reserved, must be kept at reset value.
- Page 327 RM0453 Reset and clock control (RCC) 7.4.15 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) Address offset: 0x048 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access from CPU1 is not supported.
- Page 328 Reset and clock control (RCC) RM0453 7.4.16 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) Address offset: 0x04C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access from CPU1 is not supported.
- Page 329 RM0453 Reset and clock control (RCC) 7.4.17 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) Address offset: 0x050 Reset value: 0x0208 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access from CPU1 is not supported.
- Page 330 Reset and clock control (RCC) RM0453 7.4.18 RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) Address offset: 0x058 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access from CPU1 is not supported.
- Page 331 RM0453 Reset and clock control (RCC) Bit 14 SPI2S2EN: CPU1 SPI2S2 clock enable This bit is set and cleared by software. 0: SPI2S2 clock disabled for CPU1 1: SPI2S2 clock enabled for CPU1 Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGEN: CPU1 Window watchdog clock enable This bit is set by software to enable the window watchdog clock.
- Page 332 Reset and clock control (RCC) RM0453 Bits 31:7 Reserved, must be kept at reset value. Bit 6 LPTIM3EN: CPU1 Low-power timer 3 clocks enable This bit is set and cleared by software. 0: LPTIM3 bus and kernel clocks disabled for CPU1 1: LPTIM3 bus and kernel clocks enabled for CPU1 Bit 5 LPTIM2EN: CPU1 Low-power timer 2 clocks enable Set and cleared by software.
- Page 333 RM0453 Reset and clock control (RCC) Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1EN: CPU1 SPI1 clock enable This bit is set and cleared by software. 0: SPI1 clock disabled for CPU1 1: SPI1 clock enabled for CPU1 Bit 11 TIM1EN: CPU1 TIM1 timer clock enable This bit is set and cleared by software.
- Page 334 Reset and clock control (RCC) RM0453 7.4.22 RCC AHB1 peripheral clock enable in Sleep mode register (RCC_AHB1SMENR) Address offset: 0x068 Reset value: 0x0000 1007 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res.
- Page 335 RM0453 Reset and clock control (RCC) 7.4.23 RCC AHB2 peripheral clock enable in Sleep mode register (RCC_AHB2SMENR) Address offset: 0x06C Reset value: 0x0000 0087 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res.
- Page 336 Reset and clock control (RCC) RM0453 7.4.24 RCC AHB3 peripheral clock enable in Sleep and Stop mode register (RCC_AHB3SMENR) Address offset: 0x070 Reset value: 0x0387 0000 Access: no wait state, word, half-word and byte access FLASH SRAM2 SRAM1 Res. Res. Res.
- Page 337 RM0453 Reset and clock control (RCC) Bit 17 AESSMEN: AES accelerator clock enable during CPU1 CSleep mode. This bit is set and cleared by software. 0: AES clock disabled by the clock gating during CPU1 CSleep and CStop modes 1: AES clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1 CStop mode Bit 16 PKASMEN: PKA accelerator clock enable during CPU1 CSleep mode.
- Page 338 Reset and clock control (RCC) RM0453 Bit 22 I2C2SMEN: I2C2 clock enable during CPU1 CSleep and CStop modes This bit is set and cleared by software. 0: I2C2 bus clock disabled by the clock gating during CPU1 CSleep and CStop modes 1: I2C2 bus clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1 CStop mode Bit 21 I2C1SMEN: I2C1 clock enable during CPU1 CSleep and CStop modes...
- Page 339 RM0453 Reset and clock control (RCC) 7.4.26 RCC APB1 peripheral clock enable in Sleep mode register 2 (RCC_APB1SMENR2) Address offset: 0x07C Reset value: 0x0000 0061 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res.
- Page 340 Reset and clock control (RCC) RM0453 7.4.27 RCC APB2 peripheral clock enable in Sleep mode register (RCC_APB2SMENR) Address offset: 0x080 Reset value: 0x0006 5A00 Access: word, half-word and byte access TIM17 TIM16 Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 341 RM0453 Reset and clock control (RCC) Bit 10 Reserved, must be kept at reset value. Bit 9 ADCSMEN: ADC clocks enable during CPU1 CSleep and CStop modes This bit is set and cleared by software. 0: ADC bus clock disabled by the clock gating during CPU1 CSleep and CStop modes 1: ADC bus clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1 CStop mode Bits 8:0 Reserved, must be kept at reset value.
- Page 342 Reset and clock control (RCC) RM0453 7.4.29 RCC peripherals independent clock configuration register (RCC_CCIPR) Address offset: 0x088 Reset value: 0x0000 0000 Access: no wait states, word, half-word and byte access RNGSEL[1:0] ADCSEL[1:0] Res. Res. Res. Res. LPTIM3SEL[1:0] LPTIM2SEL[1:0] LPTIM1SEL[1:0] I2C3SEL[1:0] LPUART1SEL SPI2S2SEL USART2SEL...
- Page 343 RM0453 Reset and clock control (RCC) Bits 17:16 I2C3SEL[1:0]: I2C3 clock source selection These bits are set and cleared by software to select the I2C3 clock source. 00: PCLK selected 01: System clock (SYSCLK) selected 10: HSI16 clock selected 11: Reserved Bits 15:14 I2C2SEL[1:0]: I2C2 clock source selection These bits are set and cleared by software to select the I2C2 clock source.
- Page 344 Reset and clock control (RCC) RM0453 7.4.30 RCC backup domain control register (RCC_BDCR) Address offset: 0x090 Reset value: 0x0000 0000 Reset by backup domain reset, except LSCOSEL, LSCOEN and BDRST that are reset only by backup domain power-on reset but not reset by wake-up from Standby and NRST pad. Access: 0 ≤...
- Page 345 RM0453 Reset and clock control (RCC) Bit 11 LSESYSRDY: LSE system clock ready This bit is set and cleared by hardware to indicate when the LSE system clock is ready after the LSESYSEN bit is set. This bit is only valid when LSEON, LSERDY and LSESYSEN are set.
- Page 346 Reset and clock control (RCC) RM0453 Bit 2 LSEBYP: LSE oscillator bypass This bit is set and cleared by software to bypass the LSE oscillator. It can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: LSE oscillator ready...
- Page 347 RM0453 Reset and clock control (RCC) Bit 31 LPWRRSTF: Low-power reset flag This bit is set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry. It is cleared by writing to the RMVF bit. 0: No illegal mode reset occurred 1: Illegal mode reset occurred Bit 30 WWDGRSTF: Window watchdog reset flag...
- Page 348 Reset and clock control (RCC) RM0453 Bit 15 RFRST: Sub-GHz radio reset This bit is set and cleared by software. 0: Sub-GHz radio software reset removed 1: Sub-GHz radio software reset active Bit 14 RFRSTF: Sub-GHz radio in reset status flag This bit is set and cleared by hardware.
- Page 349 RM0453 Reset and clock control (RCC) 7.4.32 RCC extended clock recovery register (RCC_EXTCFGR) Address offset: 0x108 Reset value: 0x0003 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 350 Reset and clock control (RCC) RM0453 Bits 15:8 Reserved, must be kept at reset value. Bits 7:4 C2HPRE[3:0]: HCLK2 prescaler (CPU2) These bits are set and cleared by software to control the division factor of the HCLK2 clock (CPU2). The C2HPREF flag can be checked to know if the programmed C2HPRE prescaler value is applied.
- Page 351 RM0453 Reset and clock control (RCC) 7.4.33 RCC CPU2 AHB1 peripheral clock enable register (RCC_C2AHB1ENR) Address offset: 0x148 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access from CPU2 is not supported.
- Page 352 Reset and clock control (RCC) RM0453 7.4.34 RCC CPU2 AHB2 peripheral clock enable register (RCC_C2AHB2ENR) Address offset: 0x14C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access from CPU2 is not supported.
- Page 353 RM0453 Reset and clock control (RCC) 7.4.35 RCC CPU2 AHB3 peripheral clock enable register (RCC_C2AHB3ENR) Address offset: 0x150 Reset value: 0x0208 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access from CPU2 is not supported.
- Page 354 Reset and clock control (RCC) RM0453 7.4.36 RCC CPU2 APB1 peripheral clock enable register 1 (RCC_C2APB1ENR1) Address offset: 0x158 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access from CPU2 is not supported.
- Page 355 RM0453 Reset and clock control (RCC) Bits 16:15 Reserved, must be kept at reset value. Bit 14 SPI2S2EN: CPU2 SPI2S2 clock enable This bit is set and cleared by software. 0: SPI2S2 clock disabled for CPU2 1: SPI2S2 clock enabled for CPU2 Bits 13:11 Reserved, must be kept at reset value.
- Page 356 Reset and clock control (RCC) RM0453 Bit 5 LPTIM2EN: CPU2 low-power timer 2 clocks enable This bit is set and cleared by software. 0: LPTIM2 bus and kernel clocks disabled for CPU2 1: LPTIM2 bus and kernel clocks enabled for CPU2 Bits 4:1 Reserved, must be kept at reset value.
- Page 357 RM0453 Reset and clock control (RCC) Bit 12 SPI1EN: CPU2 SPI1 clock enable This bit is set and cleared by software. 0: SPI1 clock disabled for CPU2 1: SPI1 clock enabled for CPU2 Bit 11 TIM1EN: CPU2 timer 1 clock enable This bit is set and cleared by software.
- Page 358 Reset and clock control (RCC) RM0453 7.4.40 RCC CPU2 AHB1 peripheral clock enable in Sleep mode register (RCC_C2AHB1SMENR) Address offset: 0x168 Reset value: 0x0000 1007 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res.
- Page 359 RM0453 Reset and clock control (RCC) 7.4.41 RCC CPU2 AHB2 peripheral clock enable in Sleep mode register (RCC_C2AHB2SMENR) Address offset: 0x16C Reset value: 0x0000 0087 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res.
- Page 360 Reset and clock control (RCC) RM0453 7.4.42 RCC CPU2 AHB3 peripheral clock enable in Sleep mode register (RCC_C2AHB3SMENR) Address offset: 0x170 Reset value: 0x0387 0000 Access: no wait state, word, half-word and byte access FLASH SRAM2 SRAM1 Res. Res. Res. Res.
- Page 361 RM0453 Reset and clock control (RCC) Bit 17 AESSMEN: AES accelerator clock enable during CPU2 CSleep and CStop modes This bit is set and cleared by software. 0: AES clock disabled by the clock gating during CPU2 CSleep and CStop modes 1: AES clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2 CStop mode Bit 16 PKASMEN: PKA accelerator clock enable during CPU2 CSleep and CStop modes...
- Page 362 Reset and clock control (RCC) RM0453 Bit 22 I2C2SMEN: I2C2 clock enable during CPU2 CSleep and CStop modes This bit is set and cleared by software. 0: I2C2 bus clock disabled by the clock gating during CPU2 CSleep and CStop modes 1: I2C2 bus clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2 CStop mode Bit 21 I2C1SMEN: I2C1 clock enable during CPU2 CSleep and CStop modes...
- Page 363 RM0453 Reset and clock control (RCC) 7.4.44 RCC CPU2 APB1 peripheral clock enable in Sleep mode register 2 (RCC_C2APB1SMENR2) Address offset: 0x17C Reset value: 0x0000 0061 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res.
- Page 364 Reset and clock control (RCC) RM0453 7.4.45 RCC CPU2 APB2 peripheral clock enable in Sleep mode register (RCC_C2APB2SMENR) Address offset: 0x180 Reset value: 0x0006 5A00 Access: word, half-word and byte access TIM17 TIM16 Res. Res. Res. Res. Res. Res. Res. Res.
- Page 365 RM0453 Reset and clock control (RCC) Bit 10 Reserved, must be kept at reset value. Bit 9 ADCSMEN: ADC clocks enable during CPU2 CSleep and CStop modes This bit is set and cleared by software. 0: ADC bus clock disabled by the clock gating during CPU2 CSleep and CStop modes 1: ADC bus clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2 CStop mode Bits 8:0 Reserved, must be kept at reset value.
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Page 366: Table 63. Rcc Register Map And Reset Values
Reset and clock control (RCC) RM0453 7.4.47 RCC register map Table 63. RCC register map and reset values Register Offset name RCC_CR 0x000 Reset value HSITRIM[6:0] HSICAL[7:0] MSITRIM[7:0] MSICAL[7:0] RCC_ICSCR 0x004 Reset value PPRE2[ PPRE1 HPRE[3:0] RCC_CFGR 2:0] [2:0] [1:0] [1:0] 0x008 Reset value... - Page 367 RM0453 Reset and clock control (RCC) Table 63. RCC register map and reset values (continued) Register Offset name RCC_ AHB3RSTR 0x030 Reset value Reserved 0x034 Reserved RCC_ APB1RSTR1 0x038 Reset value RCC_ APB1RSTR2 0x03C Reset value RCC_ APB2RSTR 0x040 Reset value RCC_ APB3RSTR 0x044...
- Page 368 Reset and clock control (RCC) RM0453 Table 63. RCC register map and reset values (continued) Register Offset name RCC_ APB1ENR2 0x05C Reset value RCC_ APB2ENR 0x060 Reset value RCC_ APB3ENR 0x064 Reset value RCC_ AHB1SMENR 0x068 Reset value RCC_ AHB2SMENR 0x06C Reset value RCC_...
- Page 369 RM0453 Reset and clock control (RCC) Table 63. RCC register map and reset values (continued) Register Offset name RCC_APB2 SMENR 0x080 Reset value RCC_ APB3SMENR 0x084 Reset value RCC_CCIPR 0x088 Reset value Reserved 0x08C Reserved RCC_BDCR 0x090 Reset value RCC_CSR 0x094 Reset value 0x098-...
- Page 370 Reset and clock control (RCC) RM0453 Table 63. RCC register map and reset values (continued) Register Offset name RCC_C2 AHB3ENR 0x150 Reset value Reserved 0x154 Reserved RCC_C2 APB1ENR1 0x158 Reset value RCC_C2 APB1ENR2 0x15C Reset value RCC_C2 APB2ENR 0x160 Reset value RCC_C2 APB3ENR 0x164...
- Page 371 RM0453 Reset and clock control (RCC) Table 63. RCC register map and reset values (continued) Register Offset name RCC_ C2APB1SMENR2 0x17C Reset value RCC_ C2APB2SMENR 0x180 Reset value RCC_ C2APB3SMENR 0x184 Reset value Refer to Section 2.6 for the register boundary addresses. RM0453 Rev 5 371/1450...
- Page 372 Hardware semaphore (HSEM) RM0453 Hardware semaphore (HSEM) Introduction The hardware semaphore block provides 16 (32-bit) register based semaphores. The semaphores can be used to ensure synchronization between different processes running between different cores. The HSEM provides a non-blocking mechanism to lock semaphores in an atomic way.
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Page 373: Table 64. Hsem Internal Input/Output Signals
RM0453 Hardware semaphore (HSEM) Functional description 8.3.1 HSEM block diagram As shown in Figure 33, the HSEM is based on three sub-blocks: • the semaphore block containing the semaphore status and IDs • the semaphore interface block providing AHB access to the semaphore via the HSEM_Rx and HSEM_RLRx registers •... -
Page 374: Figure 34. Procedure State Diagram
Hardware semaphore (HSEM) RM0453 The semaphore is free when its LOCK bit is 0. In this case, the COREID and PROCID are also 0. When the LOCK bit is 1, the semaphore is locked and the COREID indicates which AHB bus master ID has locked it. The PROCID indicates which process of that AHB bus master ID has locked the semaphore. - Page 375 RM0453 Hardware semaphore (HSEM) 1-step (read) lock procedure The 1-step procedure consists in a read to lock and check the semaphore in a single step, carried out from the HSEM_RLRx register. • Read lock semaphore with the AHB bus master COREID. •...
- Page 376 Hardware semaphore (HSEM) RM0453 8.3.6 HSEM COREID semaphore clear All semaphores locked by a COREID can be unlocked at once by using the HSEM_CR register. Write COREID and correct KEY value in HSEM_CR. All locked semaphores with a matching COREID are unlocked, and may generate an interrupt when enabled. Note: This procedure may be used in case of an incorrect functioning AHB bus master ID, where another AHB bus master can unlock the locked semaphores by writing the COREID of the...
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Page 377: Figure 35. Interrupt State Diagram
RM0453 Hardware semaphore (HSEM) Figure 35. Interrupt state diagram Semaphore x locked WRITE (COREID & PROCID & LOCK = 0) Interrupt Semaphore x Status = 1 Interrupt Semaphore x Enabled Interrupt Semaphore x MaskedStatus = 1 & Interrupt generated Semaphore x free MS40533V3 The procedure to get an interrupt when a semaphore becomes free is described hereafter. -
Page 378: Table 65. Authorized Ahb Bus Master Ids
Hardware semaphore (HSEM) RM0453 – If the semaphore lock fails, wait for semaphore free interrupt. Note: An interrupt does not lock the semaphore. After an interrupt, either the AHB bus master or the process must still perform the lock procedure to lock the semaphore. It is possible to have multiple AHB bus masters informed by the semaphore free interrupts. - Page 379 RM0453 Hardware semaphore (HSEM) HSEM registers Registers must be accessed using word format. Byte and half-word accesses are ignored and have no effect on the semaphores, they generate a bus error. 8.4.1 HSEM register semaphore x (HSEM_Rx) Address offset: 0x000 + 0x4 * x (x = 0 to 15) Reset value: 0x0000 0000 The HSEM_Rx must be used to perform a 2-step write lock, read back, and for unlocking a semaphore.
- Page 380 Hardware semaphore (HSEM) RM0453 8.4.2 HSEM read lock register semaphore x (HSEM_RLRx) Address offset: 0x080 + 0x4 * x (x = 0 to 15) Reset value: 0x0000 0000 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx must be used to perform a 1-step read lock.
- Page 381 RM0453 Hardware semaphore (HSEM) 8.4.3 HSEM interrupt enable register (HSEM_CnIER) Address offset: 0x100 + 0x010 * (n - 1), (n = 1 to 2) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 382 Hardware semaphore (HSEM) RM0453 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ISF[15:0]: Interrupt semaphore x status bit before enable (mask) (x = 0 to 15) This bit is set by hardware, and reset only by software. This bit is cleared by software writing the corresponding HSEM_CnICR bit.
- Page 383 RM0453 Hardware semaphore (HSEM) Bits 15:13 Reserved, must be kept at reset value. Bit 12 Reserved, must be kept at reset value. Bits 11:8 COREID[3:0]: COREID of semaphores to be cleared This field can be written by software and is always read 0. This field indicates the COREID for which the semaphores are cleared when writing the HSEM_CR.
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Page 384: Table 66. Hsem Register Map And Reset Values
Hardware semaphore (HSEM) RM0453 8.4.9 HSEM register map Table 66. HSEM register map and reset values Offset Register name COREID HSEM_R0 PROCID[7:0] 0x000 [3:0] Reset value COREID HSEM_R1 PROCID[7:0] [3:0] 0x004 Reset value COREID HSEM_R15 PROCID[7:0] [3:0] 0x03C Reset value COREID HSEM_RLR0 PROCID... - Page 385 RM0453 Hardware semaphore (HSEM) Table 66. HSEM register map and reset values (continued) Offset Register name HSEM_C2MISR MISF[15:0] 0x11C Reset value HSEM_CR KEY[15:0] COREID[3:0] 0x140 Reset value HSEM_KEYR KEY[15:0] 0x144 Reset value Refer to Section 2.6 on page 71 for the register boundary addresses. RM0453 Rev 5 385/1450...
- Page 386 Inter-processor communication controller (IPCC) RM0453 Inter-processor communication controller (IPCC) IPCC introduction The inter-processor communication controller (IPCC) is used for communicating data between two processors. The IPCC block provides a nonblocking signaling mechanism to post and retrieve communication data in an atomic way. It provides the signaling for twelve channels: •...
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Page 387: Table 67. Ipcc Interface Signals
RM0453 Inter-processor communication controller (IPCC) The channel operation mode must be known to both processors. A common parameter can be used to indicate the channel transfer mode and must also be located in a known common area. This parameter is not available from the IPCC. 9.3.1 IPCC block diagram The IPCC (see... -
Page 388: Table 68. Bits Used For The Communication
Inter-processor communication controller (IPCC) RM0453 Table 68. Bits used for the communication Processor IPCC_C1CR.TXFIE IPCC_C2CR.RXOIE IPCC_C1MR.CHnFM IPCC_C2MR.CHnOM SEND A = 1 RECEIVE B = 2 IPCC_C1SCR.CHnS IPCC_C2SCR.CHnC IPCC_C1TOC2SR.CHnF IPCC_C2CR.TXFIE IPCC_C1CR.RXOIE IPCC_C2MR.CHnFM IPCC_C1MR.CHnOM SEND A = 2 RECEIVE B = 1 IPCC_C2SCR.CHnS IPCC_C1SCR.CHnC IPCC_C2TOC1SR.CHnF... -
Page 389: Figure 38. Ipcc Simplex - Send Procedure State Diagram
RM0453 Inter-processor communication controller (IPCC) Figure 38. IPCC Simplex - Send procedure state diagram UNMASK CHnF = 1 Send Read CHnF Channel N Communication data free interrupt Write CHnFM = 0 CHnF = 0 Wait for TX free interrupt TX free interrupt free interrupt Read CHnF = 0 Write... -
Page 390: Figure 39. Ipcc Simplex - Receive Procedure State Diagram
Inter-processor communication controller (IPCC) RM0453 Figure 39. IPCC Simplex - Receive procedure state diagram occupied interrupt occupied interrupt Read CHnF = 1 MASK Channel N occupied interrupt Write CHnOM = 1 Read Communication data from Memory Complete communication retrieved Set Channel N free Write CHnC (set CHnF = 0) UNMASK Channel N... -
Page 391: Figure 40. Ipcc Half-Duplex Channel Mode Transfer Timing
RM0453 Inter-processor communication controller (IPCC) Once the processor A retrieves the response from the memory, it does not change the channel status flags. The memory location access is kept by processor A for the next communication data. Figure 40. IPCC Half-duplex channel mode transfer timing Write Write Read... -
Page 392: Figure 42. Ipcc Half-Duplex - Receive Procedure State Diagram
Inter-processor communication controller (IPCC) RM0453 To send communication data: • The sending processor waits for its response pending software variable to get 0. – Once the response pending software variable is 0 the communication data is posted. • Once the complete communication data has been posted, the channel status flag CHnF is set to occupied with CHnS and the response pending software variable is set to 1 (this gives memory access and generates the RX occupied interrupt to the receiving processor). - Page 393 RM0453 Inter-processor communication controller (IPCC) To receive the response the channel free interrupt is unmasked (CHnFM = 0): • On a TX free interrupt, the sending processor checks which channel became free, masks the associated channel free interrupt (CHnFM) and reads the response from the memory.
- Page 394 Inter-processor communication controller (IPCC) RM0453 Bit 16 TXFIE: Processor 1 transmit channel free interrupt enable Associated with IPCC_C1TOC2SR. 1: Enable an unmasked processor 1 transmit channel free to generate a TX free interrupt. 0: Processor 1 TX free interrupt disabled Bits 15:1 Reserved, must be kept at reset value.
- Page 395 RM0453 Inter-processor communication controller (IPCC) 9.4.3 IPCC processor 1 status set clear register (IPCC_C1SCR) Address offset: 0x008 Reset value: 0x0000 0000 Reading this register always returns 0x0000 0000. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CH6S CH5S CH4S CH3S CH2S...
- Page 396 Inter-processor communication controller (IPCC) RM0453 9.4.5 IPCC processor 2 control register (IPCC_C2CR) Address offset: 0x010 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TXFIE Res. Res. Res. Res. Res. Res.
- Page 397 RM0453 Inter-processor communication controller (IPCC) Bits 5:0 CHnOM: Processor 2 receive channel n occupied interrupt mask (n = 6 to 1). Associated with IPCC_C1TOC2SR.CHnF 1: Receive channel n occupied interrupt masked. 0: Receive channel n occupied interrupt not masked. 9.4.7 IPCC processor 2 status set clear register (IPCC_C2SCR) Address offset: 0x018 Reset value: 0x0000 0000...
- Page 398 Inter-processor communication controller (IPCC) RM0453 Bits 5:0 CHnF: Processor 2 transmit to processor 1 receive channel n status flag before masking (n = 6 to 1) 1: Channel occupied, data can be read by the receiving processor 1. Generates a channel RX occupied interrupt to processor 1, when unmasked. 0: Channel free, data can be written by the sending processor 2.
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Page 399: Table 69. Ipcc Register Map And Reset Values
RM0453 Inter-processor communication controller (IPCC) 9.4.9 IPCC register map Table 69. IPCC register map and reset values Register name Offset Reset value IPCC_C1CR 0x0000 Reset value IPCC_C1MR 0x0004 Reset value IPCC_C1SCR 0x0008 Reset value IPCC_C1TOC2SR 0x000C Reset value IPCC_C2CR 0x0010 Reset value IPCC_C2MR 0x0014... - Page 400 General-purpose I/Os (GPIO) RM0453 General-purpose I/Os (GPIO) 10.1 GPIO introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR) and one 32-bit set/reset register (GPIOx_BSRR). All GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).
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Page 401: Figure 43. Basic Structure Of A Standard I/O Port Bit
RM0453 General-purpose I/Os (GPIO) GPIOx_BSRR and GPIOx_BRR registers allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring between the read and the modify access. Figure 43 Figure 44 show the basic structure of a standard and a 5V-tolerant I/O port bit. -
Page 402: Table 70. Port Bit Configurations
General-purpose I/Os (GPIO) RM0453 Figure 44. Basic structure of a 5V-tolerant I/O port bit To on-chip peripheral Alternate function input on/off Read DD_FT DDIOx TTL Schmitt Protection trigger on/off diode Pull Input driver I/O pin Write Output driver DDIOx on/off Protection Pull down... - Page 403 RM0453 General-purpose I/Os (GPIO) Table 70. Port bit configurations (continued) MODE(i)[1:0] OTYPER(i) OSPEED(i)[1:0] PUPD(i)[1:0] I/O configuration Input Floating Input Input Reserved (input floating) Input/output Analog Reserved 1. GP = general purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open drain, AF = alternate function. 10.3.1 General purpose I/O (GPIO) During and just after reset, the alternate functions are not active and most of the I/O ports...
- Page 404 General-purpose I/Os (GPIO) RM0453 Specific alternate function assignments for each pin are detailed in the product datasheet. In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped on different I/O pins to optimize the number of peripherals available in smaller packages.
- Page 405 RM0453 General-purpose I/Os (GPIO) To each bit in GPIOx_ODR correspond two control bits in GPIOx_BSRR, BS(i) and BR(i): • When written to 1, BS(i) sets the corresponding ODR(i) bit. • When written to 1, BR(i) resets the ODR(i) corresponding bit. Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in GPIOx_ODR.
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Page 406: Figure 45. Input Floating/Pull-Up/Pull-Down Configurations
General-purpose I/Os (GPIO) RM0453 10.3.9 Input configuration When the I/O port is programmed as input, the following occurs: • The output buffer is disabled. • The Schmitt trigger input is activated. • The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register. -
Page 407: Figure 46. Output Configuration
RM0453 General-purpose I/Os (GPIO) The figure below shows the output configuration of the I/O port bit. Figure 46. Output configuration Read DDIOx TTL Schmitt DDIOx trigger on/off protection Write Input driver diode pull I/O pin Output driver DDIOx on/off P-MOS protection pull down... -
Page 408: Figure 48. High Impedance Analog Configuration
General-purpose I/Os (GPIO) RM0453 10.3.12 Analog configuration When the I/O port is programmed as analog configuration, the following occurs: • The output buffer is disabled. • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). •... - Page 409 RM0453 General-purpose I/Os (GPIO) 10.3.15 Using PH3 as GPIO PH3 may be used as boot pin (BOOT0) or as GPIO. PH3 switches from the input mode to the analog input mode depending on the nSWBOOT0 bit in the user option byte as follows: •...
- Page 410 General-purpose I/Os (GPIO) RM0453 10.4.2 GPIOx output type register (GPIOx_OTYPER) (x = A to B) Address offset: Block A: 0x0004 Address offset: Block B: 0x0404 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 411 RM0453 General-purpose I/Os (GPIO) 10.4.4 GPIOx pull-up/pull-down register (GPIOx_PUPDR) (x = A to B) Address offset: Block A: 0x000C Address offset: Block B: 0x040C Reset value: Block A: 0x6400 0000 Reset value: Block B: 0x0000 0100 PUPD15[1:0] PUPD14[1:0] PUPD13[1:0] PUPD12[1:0] PUPD11[1:0] PUPD10[1:0] PUPD9[1:0]...
- Page 412 General-purpose I/Os (GPIO) RM0453 10.4.6 GPIOx output data register (GPIOx_ODR) (x = A to B) Address offset: Block A: 0x0014 Address offset: Block B: 0x0414 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 413 RM0453 General-purpose I/Os (GPIO) 10.4.8 GPIOx configuration lock register (GPIOx_LCKR) (x = A to B) Address offset: Block A: 0x001C Address offset: Block B: 0x041C Reset value: 0x0000 0000 This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK).
- Page 414 General-purpose I/Os (GPIO) RM0453 10.4.9 GPIOx alternate function low register (GPIOx_AFRL) (x = A to B) Address offset: Block A: 0x0020 Address offset: Block B: 0x0420 Reset value: 0x0000 0000 AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0] Bits 31:0 AFSELy[3:0]: Port Pxy alternate function selection (y = 7 to 0) These bits are written by software to configure alternate function I/Os 0x0: AF0 selected 0x1: AF1 selected...
- Page 415 RM0453 General-purpose I/Os (GPIO) 10.4.11 GPIOx bit reset register (GPIOx_BRR) (x = A to B) Address offset: Block A: 0x0028 Address offset: Block B: 0x0428 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 416 General-purpose I/Os (GPIO) RM0453 Bits 5:4 MODE2[1:0]: Port PC2 IO type configuration Bits 3:2 MODE1[1:0]: Port PC1 IO type configuration Bits 1:0 MODE0[1:0]: Port PC0 IO type configuration These bits are written by software to configure the I/O mode. 00: Input mode 01: General purpose output mode 10: Alternate function mode 11: Analog mode (reset state)
- Page 417 RM0453 General-purpose I/Os (GPIO) Bits 13:12 OSPEED6[1:0]: Port PC6 output speed configuration Bits 11:10 OSPEED5[1:0]: Port PC5 output speed configuration Bits 9:8 OSPEED4[1:0]: Port PC4 output speed configuration Bits 7:6 OSPEED3[1:0]: Port PC3 output speed configuration Bits 5:4 OSPEED2[1:0]: Port PC2 output speed configuration Bits 3:2 OSPEED1[1:0]: Port PC1 output speed configuration Bits 1:0 OSPEED0[1:0]: Port PC0 output speed configuration These bits are written by software to configure the I/O output speed.
- Page 418 General-purpose I/Os (GPIO) RM0453 10.4.16 GPIOC input data register (GPIOC_IDR) Address offset: 0x0810 Reset value: 0x0000 XXXX Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ID15 ID14 ID13 Res. Res. Res. Res. Res.
- Page 419 RM0453 General-purpose I/Os (GPIO) 10.4.18 GPIOC bit set/reset register (GPIOC_BSRR) Address offset: 0x0818 Reset value: 0x0000 0000 BR15 BR14 BR13 Res. Res. Res. Res. Res. Res. rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 BS15 BS14 BS13 Res. Res.
- Page 420 General-purpose I/Os (GPIO) RM0453 10.4.19 GPIOC configuration lock register (GPIOC_LCKR) Address offset: 0x081C Reset value: 0x0000 0000 This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO.
- Page 421 RM0453 General-purpose I/Os (GPIO) 10.4.20 GPIOC alternate function low register (GPIOC_AFRL) Address offset: 0x0820 Reset value: 0x0000 0000 Res. Res. Res. Res. AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 AFSEL6[3:0]: Port PC6 alternate function selection Bits 23:20 AFSEL5[3:0]: Port PC5 alternate function selection Bits 19:16 AFSEL4[3:0]: Port PC4 alternate function selection Bits 15:12 AFSEL3[3:0]: Port PC3 alternate function selection...
- Page 422 General-purpose I/Os (GPIO) RM0453 Bits 23:20 AFSEL13[3:0]: Port PC13 alternate function selection These bits are written by software to configure alternate function I/Os. 0x0: AF0 selected 0x1: AF1 selected 0x2: AF2 selected 0xE: AF14 selected 0xF: AF15 selected Bits 19:0 Reserved, must be kept at reset value. 10.4.22 GPIOC bit reset register (GPIOC_BRR) Address offset: 0x0828...
- Page 423 RM0453 General-purpose I/Os (GPIO) Bits 7:6 MODE3[1:0]: Port PH3 IO type configuration These bits are written by software to configure the I/O mode. 00: Input mode 01: General purpose output mode 10: Alternate function mode 11: Analog mode (reset state) Bits 5:0 Reserved, must be kept at reset value.
- Page 424 General-purpose I/Os (GPIO) RM0453 Bits 7:6 OSPEED3[1:0]: Port PH3 output speed configuration These bits are written by software to configure the I/O output speed. 00: Low speed 01: Medium speed 10: Fast speed 11: High speed Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.
- Page 425 RM0453 General-purpose I/Os (GPIO) 10.4.28 GPIOH output data register (GPIOH_ODR) Address offset: 0x1C14 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 426 General-purpose I/Os (GPIO) RM0453 10.4.30 GPIOH configuration lock register (GPIOH_LCKR) Address offset: 0x1C1C Reset value: 0x0000 0000 This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO.
- Page 427 RM0453 General-purpose I/Os (GPIO) 10.4.31 GPIOH alternate function low register (GPIOH_AFRL) Address offset: 0x1C20 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AFSEL3[3:0] Res. Res. Res. Res. Res. Res.
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Page 428: Table 71. Gpioa Register Map And Reset Values
General-purpose I/Os (GPIO) RM0453 10.4.33 GPIOA register map Table 71. GPIOA register map and reset values Offset Register name GPIOA_MODER 0x0000 Reset value GPIOA_OTYPER 0x0004 Reset value GPIOA_OSPEEDR 0x0008 Reset value GPIOA_PUPDR 0x000C Reset value GPIOA_IDR 0x0010 Reset value GPIOA_ODR 0x0014 Reset value GPIOA_BSRR... -
Page 429: Table 72. Gpiob Register Map And Reset Values
RM0453 General-purpose I/Os (GPIO) 10.4.34 GPIOB register map Table 72. GPIOB register map and reset values Offset Register name GPIOB_MODER 0x0400 Reset value GPIOB_OTYPER 0x0404 Reset value GPIOB_OSPEEDR 0x0408 Reset value GPIOB_PUPDR 0x040C Reset value GPIOB_IDR 0x0410 Reset value GPIOB_ODR 0x0414 Reset value GPIOB_BSRR... -
Page 430: Table 73. Gpioc Register Map And Reset Values
General-purpose I/Os (GPIO) RM0453 10.4.35 GPIOC register map Table 73. GPIOC register map and reset values Offset Register name GPIOC_MODER 0x0800 Reset value GPIOC_OTYPER 0x0804 Reset value GPIOC_OSPEEDR 0x0808 Reset value GPIOC_PUPDR 0x080C Reset value GPIOC_IDR 0x0810 Reset value GPIOC_ODR 0x0814 Reset value GPIOC_BSRR... -
Page 431: Table 74. Gpioh Register Map And Reset Values
RM0453 General-purpose I/Os (GPIO) 10.4.36 GPIOH register map Table 74. GPIOH register map and reset values Offset Register name GPIOH_MODER 0x1C00 Reset value GPIOH_OTYPER 0x1C04 Reset value GPIOH_OSPEEDR 0x1C08 Reset value GPIOH_PUPDR 0x1C0C Reset value GPIOH_IDR 0x1C10 Reset value GPIOH_ODR 0x1C14 Reset value GPIOH_BSRR... - Page 432 System configuration controller (SYSCFG) RM0453 System configuration controller (SYSCFG) 11.1 SYSCFG main features STM32WL5x devices feature a set of configuration registers. The main purposes of the system configuration controller are the following: • Remapping memory areas • Managing the external interrupt line connection to the GPIOs •...
- Page 433 RM0453 System configuration controller (SYSCFG) 11.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1) Address offset: 0x004 Reset value: 0x7C00 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 434 System configuration controller (SYSCFG) RM0453 Bit 8 BOOSTEN: I/O analog switch voltage booster enable 0: I/O analog switches are supplied by V voltage. This is the recommended configuration when using the ADC in high V voltage operation. 1: I/O analog switches are supplied by a dedicated voltage booster (supplied by V ).
- Page 435 RM0453 System configuration controller (SYSCFG) Bits 2:0 EXTI0[2:0]: EXTI0 configuration bits These bits are written by software to select the source input for the EXTI0 external interrupt. 000: PA0 pin 001: PB0 pin 010: PC0 pin Others: Reserved Note: Some of the I/O pins mentioned in this register may not be available on small packages. 11.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
- Page 436 System configuration controller (SYSCFG) RM0453 Bits 2:0 EXTI4[2:0]: EXTI4 configuration bits These bits are written by software to select the source input for the EXTI4 external interrupt. 000: PA4 pin 001: PB4 pin 010: PC4 pin Others: Reserved Note: Some of the I/O pins mentioned in this register may not be available on small packages. 11.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
- Page 437 RM0453 System configuration controller (SYSCFG) Note: Some of the I/O pins mentioned in this register may not be available on small packages. 11.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x014 Reset value: 0x0000 0000 Res. Res. Res. Res.
- Page 438 System configuration controller (SYSCFG) RM0453 11.2.7 SYSCFG SRAM control and status register (SYSCFG_SCSR) Address offset: 0x18 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PKASR SRAM SRAM2 Res. Res.
- Page 439 RM0453 System configuration controller (SYSCFG) Bits 7:4 Reserved, must be kept at reset value. Bit 3 ECCL: ECC lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the flash ECC error connection to TIM1/16/17 break input. 0: ECC error disconnected from TIM1/16/17 break input.
- Page 440 System configuration controller (SYSCFG) RM0453 11.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR) Address offset: 0x024 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 441 RM0453 System configuration controller (SYSCFG) 11.2.12 SYSCFG CPU1 interrupt mask register 2 (SYSCFG_IMR2) Address offset: 0x104 Reset value: 0x0000 0000 PVM3I Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PVDIM Res. Res. Res. Res. Res. Res. Res. Res.
- Page 442 System configuration controller (SYSCFG) RM0453 Bit 12 ADCIM: ADC interrupt mask to CPU2 0: ADC interrupt forwarded to CPU2 1. ADC interrupt to CPU2 masked Bit 11 COMPIM: COMP interrupt mask to CPU2 0: COMP interrupt forwarded to CPU2 1. COMP interrupt to CPU2 masked. Bit 10 AESIM: AES interrupt mask to CPU2 0: AES interrupt forwarded to CPU2 1.
- Page 443 RM0453 System configuration controller (SYSCFG) 11.2.14 SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2) Address offset: 0x10C Reset value: 0x0000 0000 PVM3I Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PVDIM Res. Res. Res. DMAM DMA2C DMA2C DMA2C DMA2C DMA2C DMA2C...
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Page 444: Table 75. Syscfg Register Map And Reset Values
System configuration controller (SYSCFG) RM0453 Bits 31:1 Reserved, must be kept at reset value. Bit 0 RFTBSEL: radio debug test bus selection 0 Digital test bus selected on RF_ADTB[3:0] 1: Analog test bus selected on RF_ADTB[3:0] 11.2.16 SYSCFG register map Table 75. - Page 445 RM0453 System configuration controller (SYSCFG) Table 75. SYSCFG register map and reset values (continued) Offset Register name SYSCFG_IMR1 0x100 Reset value SYSCFG_IMR2 0x104 Reset value SYSCFG_C2IMR1 0x108 Reset value SYSCFG_C2IMR2 0x10C Reset value 0x110 to Reserved Reserved 0x204 SYSCFG_RFDCR 0x208 Reset value Refer to Section 2.6...
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Page 446: Table 76. Stm32Wl5X Peripherals Interconnect Matrix
Peripherals interconnect matrix RM0453 Peripherals interconnect matrix 12.1 Introduction Several peripherals have direct connections between them, enabling autonomous communication and/or synchronization between them. This saves CPU resources and, consequently power consumption. In addition, these hardware connections remove software latency and result in more predictable system design. Depending on peripherals, these interconnections can operate in Run, Sleep, LPRun, LPSleep, Stop 0, Stop 1 and Stop 2 modes. - Page 447 RM0453 Peripherals interconnect matrix (1) (2) Table 76. STM32WL5x peripherals interconnect matrix (continued) Destination Source COMP1 COMP2 SYST ERR 1. Numbers in this table are links to corresponding subsections of Section 12.3: Interconnection details. The “-” symbol in grayed cells means no interconnect. 12.3 Interconnection details 12.3.1...
- Page 448 Peripherals interconnect matrix RM0453 12.3.2 From timer (LPTIM1/LPTIM2) to timer (LPTIM3) Purpose Some timers are linked together internally for synchronization or chaining. When one timer is configured in Master mode, it can reset, start, stop or clock the counter of another timer configured in Slave mode.
- Page 449 RM0453 Peripherals interconnect matrix 12.3.4 From timer (LPTIM1/LPTIM2) to DAC Purpose Low-power timer LPTIM1/LPTIM2 can be used to generate an DAC trigger event. DAC triggering is described in Section 19.4.7: DAC trigger selection. Triggering signals The output from low-power timer is on signals LPTIMx_OUT event. The input to DAC is on signals dac_ch1_trg[15:0].
- Page 450 Peripherals interconnect matrix RM0453 External clock LSE can be used as input to general-purpose timers (TIM2) on TIM2_ETR pin (see TIM2 option register 1 (TIM2_OR1)). Active power modes Run, Sleep, LPRun, LPSleep 12.3.7 From RTC, TAMP, COMP1, COMP2 to low-power timers (LPTIM1/LPTIM2) Purpose RTC alarm A/B, TAMP_IN1/2/3 input detection and COMP1/2_OUT can be used as trigger...
- Page 451 RM0453 Peripherals interconnect matrix 12.3.9 From internal analog to ADC Purpose Internal temperature sensor (V ), Internal reference voltage (V ) and V monitoring REFINT channel are connected to ADC input channel. This is according to the following sections: • Section 18.2: ADC main features •...
- Page 452 Peripherals interconnect matrix RM0453 12.3.11 From system errors to timers (TIM1/TIM16/TIM17) Purpose CSS, CPU hard fault, RAM parity error, FLASH ECC double error detection and PVD can generate system errors in the form of timer break toward timers (TIM1/TIM16/TIM17). The purpose of the break function is to protect power switches driven by PWM signals generated by the timers.
- Page 453 RM0453 Peripherals interconnect matrix 12.3.14 From timer (LPTIM3) to sub-GHz radio SPI NSS Purpose Low-power timer LPTIM3 can be used to generate a sub-GHz radio SPI NSS event. Triggering signals The output from low-power timer is on signal LPTIM3_OUT event. The connection between timers and sub-GHz radio SPI NSS is provided in PWR sub-GHz SPI control register...
- Page 454 Direct memory access controller (DMA) RM0453 Direct memory access controller (DMA) 13.1 Introduction The direct memory access (DMA) controller is a bus master and system peripheral. The DMA is used to perform programmable data transfers between memory-mapped peripherals and/or memories, upon the control of an off-loaded CPU. The DMA controller features a single AHB master architecture.
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Page 455: Table 77. Dma1 And Dma2 Implementation
RM0453 Direct memory access controller (DMA) 13.3 DMA implementation 13.3.1 DMA1 and DMA2 DMA1 and DMA2 are implemented with the hardware configuration parameters shown Table Table 77. DMA1 and DMA2 implementation Feature DMA1 DMA2 Number of channels Security 1 (supported) 1 (supported) 13.3.2 DMA request mapping... -
Page 456: Figure 49. Dma Block Diagram
Direct memory access controller (DMA) RM0453 13.4 DMA functional description 13.4.1 DMA block diagram The DMA block diagram is shown in Figure Figure 49. DMA block diagram DMA1 Ch 1 Ch 2 AHB master interface Ch 7 dma1_req [1..7] Arbiter dma1_ack [1..7] dma1_secm [1..7] dma1_priv[1..7]... -
Page 457: Table 78. Dma Internal Input/Output Signals
RM0453 Direct memory access controller (DMA) The DMA controller performs direct memory transfer by sharing the AHB system bus with other system masters. The bus matrix implements round-robin scheduling. DMA requests may stop the CPU access to the system bus for a number of bus cycles, when CPU and DMA target the same destination (memory or peripheral). - Page 458 Direct memory access controller (DMA) RM0453 The request/acknowledge protocol is used when a peripheral is either the source or the destination of the transfer. For example, in case of memory-to-peripheral transfer, the peripheral initiates the transfer by driving its single request signal to the DMA controller. The DMA controller reads then a single data in the memory and writes this data to the peripheral.
- Page 459 RM0453 Direct memory access controller (DMA) 13.4.5 DMA channels Each channel may handle a DMA transfer between a peripheral register located at a fixed address, and a memory address. The amount of data items to transfer is programmable. The register that contains the amount of data items to transfer is decremented after each transfer.
- Page 460 Direct memory access controller (DMA) RM0453 When a channel x is configured in secure mode, the following access controls rules are applied: • A non-secure read access to a register field of this channel is forced to return 0, except for both the secure state and the privileged state of this channel x (SECM and PRIV bits of the DMA_CCRx register) which are readable by a non-secure software.
- Page 461 RM0453 Direct memory access controller (DMA) When a channel is configured in a privileged (or unprivileged) mode, the AHB master transfers from the source and to the destination, are privileged (respectively unprivileged). DMA generates a privileged bus, dma_priv[7:0], reflecting the PRIV bit of the DMA_CCRx register, in order to keep the other hardware peripherals, like DMAMUX, informed of the privileged / unprivileged state of each DMA channel x.
- Page 462 Direct memory access controller (DMA) RM0453 The three following use cases may happen: • Suspend and resume a channel This corresponds to the two following actions: – An active channel is disabled by software (writing DMA_CCRx.EN = 0 whereas DMA_CCRx.EN = 1). –...
- Page 463 RM0453 Direct memory access controller (DMA) Memory-to-memory mode The DMA channels may operate without being triggered by a request from a peripheral. This mode is called memory-to-memory mode, and is initiated by software. If the MEM2MEM bit in the DMA_CCRx register is set, the channel, if enabled, initiates transfers.
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Page 464: Table 79. Programmable Data Width And Endian Behavior (When Pinc = Minc = 1)
Direct memory access controller (DMA) RM0453 13.4.6 DMA data width, alignment and endianness When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data alignments as described in Table Table 79. Programmable data width and endian behavior (when PINC = MINC = 1) Source Destinat Destination... - Page 465 RM0453 Direct memory access controller (DMA) Addressing AHB peripherals not supporting byte/half-word write transfers When the DMA controller initiates an AHB byte or half-word write transfer, the data are duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]). When the AHB slave peripheral does not support byte or half-word write transfers and does not generate any error, the DMA controller writes the 32 HWDATA bits as shown in the two examples below:...
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Page 466: Table 80. Dma Interrupt Requests
Direct memory access controller (DMA) RM0453 13.5 DMA interrupts An interrupt can be generated on a half transfer, transfer complete or transfer error for each DMA channel x (whatever the channel is secure or non-secure). Separate interrupt enable bits are available for flexibility. Table 80. - Page 467 RM0453 Direct memory access controller (DMA) Bits 31:28 Reserved, must be kept at reset value. Bit 27 TEIF7: Transfer error (TE) flag for channel 7 0: No TE event 1: A TE event occurred. Bit 26 HTIF7: Half transfer (HT) flag for channel 7 0: No HT event 1: An HT event occurred.
- Page 468 Direct memory access controller (DMA) RM0453 Bit 13 TCIF4: Transfer complete (TC) flag for channel 4 0: No TC event 1: A TC event occurred. Bit 12 GIF4: Global interrupt flag for channel 4 0: No TE, HT, or TC event 1:A TE, HT, or TC event occurred.
- Page 469 RM0453 Direct memory access controller (DMA) 13.6.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 This register may mix secure and non-secure information, depending on the secure mode of each channel (SECM bit of the DMA_CCRx register). A secure software is able to set any flag clear bit of the DMA_IFCR, and order DMA hardware to clear any corresponding flag(s) in the DMA_ISR register.
- Page 470 Direct memory access controller (DMA) RM0453 Bit 20 CGIF6: Global interrupt flag clear for channel 6 Bit 19 CTEIF5: Transfer error flag clear for channel 5 Bit 18 CHTIF5: Half transfer flag clear for channel 5 Bit 17 CTCIF5: Transfer complete flag clear for channel 5 Bit 16 CGIF5: Global interrupt flag clear for channel 5 Bit 15 CTEIF4: Transfer error flag clear for channel 4 Bit 14 CHTIF4: Half transfer flag clear for channel 4...
- Page 471 RM0453 Direct memory access controller (DMA) Setting any of the DSEC or SSEC bits must be performed by a secure write access to this register. Except SECM and PRIV control bits, any other register field is non-readable by a non-secure software if the SECM bit is set, and non-readable by an unprivileged software if the PRIV bit is set.
- Page 472 Direct memory access controller (DMA) RM0453 Bit 18 SSEC: Security of the DMA transfer from the source This bit can only be accessed - read, set or cleared - by a secure software. It must be a privileged software if the channel is in privileged mode. This bit is cleared by hardware when the securely written data bit 17 is cleared (on a secure reconfiguration of the channel as non -secure).
- Page 473 RM0453 Direct memory access controller (DMA) Bits 11:10 MSIZE[1:0]: Memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0.
- Page 474 Direct memory access controller (DMA) RM0453 Bit 6 PINC: Peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0.
- Page 475 RM0453 Direct memory access controller (DMA) Bit 2 HTIE: Half transfer interrupt enable 0: Disabled 1: Enabled Note: This bit is set and cleared by software (privileged/secure software if the channel is in privileged/secure mode). It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
- Page 476 Direct memory access controller (DMA) RM0453 13.6.5 DMA channel x peripheral address register (DMA_CPARx) Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 7) Reset value: 0x0000 0000 PA[31:16] PA[15:0] Bits 31:0 PA[31:0]: Peripheral address It contains the base address of the peripheral data register from/to which the data is read/written.
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Page 477: Table 81. Dma Register Map And Reset Values
RM0453 Direct memory access controller (DMA) Bits 31:0 MA[31:0]: Peripheral address It contains the base address of the memory from/to which the data is read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. - Page 478 Direct memory access controller (DMA) RM0453 Table 81. DMA register map and reset values (continued) Offset Register name DMA_CCR3 0x030 Reset value DMA_CNDTR3 NDT[17:0] 0x034 Reset value DMA_CPAR3 PA[31:0] 0x038 Reset value DMA_CMAR3 MA[31:0] 0x03C Reset value 0x040 Reserved Reserved. DMA_CCR4 0x044 Reset value...
- Page 479 RM0453 Direct memory access controller (DMA) Table 81. DMA register map and reset values (continued) Offset Register name DMA_CNDTR7 NDT[17:0] 0x084 Reset value DMA_CPAR7 PA[31:0] 0x088 Reset value DMA_CMAR7 MA[31:0] 0x08C Reset value Refer to Section 2.6 for the register boundary addresses. RM0453 Rev 5 479/1450...
- Page 480 DMA request multiplexer (DMAMUX) RM0453 DMA request multiplexer (DMAMUX) 14.1 Introduction A peripheral indicates a request for DMA transfer by setting its DMA request signal. The DMA request is pending until served by the DMA controller that generates a DMA acknowledge signal, and the corresponding DMA request signal is deasserted.
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Page 481: Table 82. Dmamux Instantiation
RM0453 DMA request multiplexer (DMAMUX) 14.2 DMAMUX main features • 14-channel programmable DMA request line multiplexer output • 4-channel DMA request generator • 21 trigger inputs to DMA request generator • 21 synchronization inputs • Per DMA request generator channel: –... -
Page 482: Table 83. Dmamux1: Assignment Of Multiplexer Inputs To Resources
DMA request multiplexer (DMAMUX) RM0453 Table 82. DMAMUX instantiation (continued) Feature DMAMUX1 Number of DMAMUX synchronization inputs Number of DMAMUX peripheral request inputs DMAMUX security support 14.3.2 DMAMUX1 mapping The mapping of resources to DMAMUX1 is hardwired. DMAMUX1 is used with DMA1 and DMA2 •... -
Page 483: Table 84. Dmamux1: Assignment Of Trigger Inputs To Resources
RM0453 DMA request multiplexer (DMAMUX) Table 84. DMAMUX1: assignment of trigger inputs to resources Trigger input Resource Trigger input Resource EXTI LINE0 dmamux_evt0 EXTI LINE1 dmamux_evt1 EXTI LINE2 LPTIM1_OUT EXTI LINE3 LPTIM2_OUT EXTI LINE4 LPTIM3_OUT EXTI LINE5 Reserved EXTI LINE6 Reserved EXTI LINE7 Reserved... -
Page 484: Figure 50. Dmamux Block Diagram
DMA request multiplexer (DMAMUX) RM0453 14.4 DMAMUX functional description 14.4.1 DMAMUX block diagram Figure 50 shows the DMAMUX block diagram. Figure 50. DMAMUX block diagram 32-bit AHB bus dmamux_hclk DMAMUX Request multiplexer To secure AHB slave interrupt Channel m interface controller: DMAMUX_CmCR dmamux_ilac... -
Page 485: Table 86. Dmamux Signals
RM0453 DMA request multiplexer (DMAMUX) 14.4.2 DMAMUX signals Table 86 lists the DMAMUX signals. Table 86. DMAMUX signals Signal name Description dmamux_hclk DMAMUX AHB clock dmamux_req_inx DMAMUX DMA request line inputs from peripherals dmamux_trgx DMAMUX DMA request triggers inputs (to request generator sub-block) dmamux_req_genx DMAMUX request generator sub-block channels outputs DMAMUX request multiplexer sub-block inputs (from peripheral... - Page 486 DMA request multiplexer (DMAMUX) RM0453 14.4.4 DMAMUX secure/non-secure channels The DMAMUX is a security-aware peripheral , partitioning all its resources so that they exist in one of the two worlds: the secure world and the normal/non-secure world, at any given time.
- Page 487 RM0453 DMA request multiplexer (DMAMUX) A DMA request is sourced either from the peripherals, or from the DMAMUX request generator. The DMAMUX request line multiplexer channel x selects the DMA request line number as configured by the DMAREQ_ID field in the DMAMUX_CxCR register. Note: The null value in the field DMAREQ_ID corresponds to no DMA request line selected.
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Page 488: Figure 51. Synchronization Mode Of The Dmamux Request Line Multiplexer Channel
DMA request multiplexer (DMAMUX) RM0453 Figure 51. Synchronization mode of the DMAMUX request line multiplexer channel Selected DMA request line transferred to the output DMA requests served DMA request pending Selected dmamux_reqx Not pending dmamux_syncx dmamux_req_outx DMA request counter dmamux_evtx DMA request counter underrun Synchronization event DMA request counter auto-reload to NBREQ... - Page 489 RM0453 DMA request multiplexer (DMAMUX) Note: If EGE is enabled and NBREQ = 0, an event is generated after each served DMA request. Note: A synchronization event (edge) is detected if the state following the edge remains stable for more than two AHB clock cycles. Upon writing into DMAMUX_CxCR register, the synchronization events are masked during three AHB clock cycles.
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Page 490: Table 87. Dmamux Interrupts
DMA request multiplexer (DMAMUX) RM0453 Note: The GNBREQ field value can be written by software only when the enable GE bit of the corresponding generator channel x is disabled. There is no hardware write protection. A trigger event (edge) is detected if the state following the edge remains stable for more than two AHB clock cycles. - Page 491 RM0453 DMA request multiplexer (DMAMUX) Table 87. DMAMUX interrupts (continued) Interrupt signal Interrupt event Event flag Clear bit Enable bit Synchronization event overrun on a secure channel x of the SOFx CSOFx SOIE DMAMUX request line multiplexer dmamux_sec_ovr_it Trigger event overrun on a secure channel x of the COFx DMAMUX request generator...
- Page 492 DMA request multiplexer (DMAMUX) RM0453 14.6 DMAMUX registers Refer to the table containing register boundary addresses for the DMAMUX base address. DMAMUX registers may be accessed per byte (8-bit), half-word (16-bit), or word (32-bit). The address must be aligned with the data size. 14.6.1 DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR)
- Page 493 RM0453 DMA request multiplexer (DMAMUX) Bit 9 EGE: Event generation enable 0: Event generation disabled 1: Event generation enabled Bit 8 SOIE: Synchronization overrun interrupt enable 0: Interrupt disabled 1: Interrupt enabled Bits 7:0 DMAREQ_ID[7:0]: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.
- Page 494 DMA request multiplexer (DMAMUX) RM0453 depending on the privileged control bit of the connected DMA controller channel y, and considering that the DMAMUX x channel output is connected to the y channel of the DMA (refer to the DMAMXUX mapping implementation section). Res.
- Page 495 RM0453 DMA request multiplexer (DMAMUX) Bits 18:17 GPOL[1:0]: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input 00: No event, i.e. no trigger detection nor generation. 01: Rising edge 10: Falling edge 11: Rising and falling edges Bit 16 GE: DMA request generator channel x enable 0: DMA request generator channel x disabled 1: DMA request generator channel x enabled...
- Page 496 DMA request multiplexer (DMAMUX) RM0453 14.6.6 DMAMUX request generator interrupt clear flag register (DMAMUX_RGCFR) Address offset: 0x144 Reset value: 0x0000 0000 This register must be written at bit level by a non-secure or secure write, according to the secure mode of the considered DMAMUX request line multiplexer channel y it is assigned to, and considering that the DMAMUX request generator x channel output is selected by the y channel of the DMAMUX request line channel (refer to DMAMUX_CyCR.DMAREQ_ID[7:0] and to the DMAMXUX mapping implementation...
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Page 497: Table 88. Dmamux Register Map And Reset Values
RM0453 DMA request multiplexer (DMAMUX) 14.6.7 DMAMUX register map The following table summarizes the DMAMUX registers and reset values. Refer to the register boundary address table for the DMAMUX register base address. Table 88. DMAMUX register map and reset values Offset Register DMAREQ_ID[6:0]... - Page 498 DMA request multiplexer (DMAMUX) RM0453 Table 88. DMAMUX register map and reset values (continued) Offset Register 0x088 - Reserved 0x0FC DMAMUX_RG0CR GNBREQ[4:0] SIG_ID[4:0] 0x100 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAMUX_RG1CR GNBREQ[4:0] SIG_ID[4:0] 0x104...
- Page 499 RM0453 Nested vectored interrupt controller (NVIC) Nested vectored interrupt controller (NVIC) 15.1 NVIC main features CPU1 NVIC features: • 62 maskable interrupt channels (not including the sixteen Cortex-M4 with DSP interrupt lines) • 16 programmable priority levels (four bits of interrupt priority used) •...
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Page 500: Table 89. Cpu1 Vector Table
Nested vectored interrupt controller (NVIC) RM0453 The interrupt block diagram is shown in the figure below. Figure 53. Interrupt block diagram Peripheral CPU1 interrupt Peripheral interrupt NVIC AIEC interrupt SYSCFG interrupt CPU2 Peripheral C1IMRn interrupt Peripheral C2IMRn NVIC interrupt Peripheral interrupt MSv60391V1 15.3... - Page 501 RM0453 Nested vectored interrupt controller (NVIC) Table 89. CPU1 vector table (continued) Type of (1)(2) Acronym Description Address priority Settable PendSV Pendable request for system service 0x0000 0038 Settable SysTick SysTick timer 0x0000 003C Settable WWDG Window watchdog early wake-up 0x0000 0040 PVD, PVD through EXTI[16] (IMR2[20])
- Page 502 Nested vectored interrupt controller (NVIC) RM0453 Table 89. CPU1 vector table (continued) Type of (1)(2) Acronym Description Address priority 27 34 Settable TIM2 Timer 2 global interrupt 0x0000 00AC 28 35 Settable TIM16 Timer 16 global interrupt 0x0000 00B0 29 36 Settable TIM17 Timer 17 global interrupt 0x0000 00B4...
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Page 503: Table 90. Cpu2 Vector Table
RM0453 Nested vectored interrupt controller (NVIC) Table 89. CPU1 vector table (continued) Type of (1)(2) Acronym Description Address priority 59 66 Settable DMA2_CH6 DMA2 channel 6 non-secure interrupt 0x0000 012C 60 67 Settable DMA2_CH7 DMA2 channel 7 non-secure interrupt 0x0000 0130 61 68 Settable DMAMUX1_OVR DMAMUX1 overrun interrupt... - Page 504 Nested vectored interrupt controller (NVIC) RM0453 Table 90. CPU2 vector table (continued) Type of (1)(2) Acronym Description Address priority Settable EXTI[15:4] EXTI line 15:4 interrupt through EXTI[15:4] (C2IMR1[31:20]) 0x0000 0058 COMP, COMP1 and COMP2 interrupt through EXTI[22:21] (C2IMR1[11]) 10 Settable 0x0000 005C ADC, ADC global interrupt (C2IMR1[12])
- Page 505 RM0453 Nested vectored interrupt controller (NVIC) Table 90. CPU2 vector table (continued) Type of (1)(2) Acronym Description Address priority 28 31 Settable USART2 USART2 global interrupt 0x0000 00B0 29 32 Settable LPUART1 LPUART1 global interrupt 0x0000 00B4 30 33 Settable SUBGHZSPI Sub-GHz radio SPI global interrupt 0x0000 00B8...
- Page 506 Extended interrupts and event controller (EXTI) RM0453 Extended interrupts and event controller (EXTI) The extended interrupts and event controller (EXTI) manages the individual CPU and system wake-up through configurable and direct event inputs. It provides wake-up requests to the power control and generates an interrupt request to the CPU NVIC and events to the CPU event input.
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Page 507: Table 91. Exti Pin Overview
RM0453 Extended interrupts and event controller (EXTI) The masking block provides the event input distribution to the different wake-up, interrupt and event outputs, and the masking of these. Figure 54. EXTI block diagram AHB interface Registers hclk sys_wakeup c1_wakeup c2_wakeup it_exti_per(y) Wakeup Direct event(x) or... -
Page 508: Table 93. Wake-Up Interrupts
Extended interrupts and event controller (EXTI) RM0453 16.3 EXTI connections between peripherals and CPU The peripherals able to generate wake-up or interrupt events when the system is in Stop mode, are connected to the EXTI. Peripheral wake-up signals that generate a pulse or that do not have an interrupt status bits in the peripheral, are connected to an EXTI configurable event input. - Page 509 RM0453 Extended interrupts and event controller (EXTI) Table 93. Wake-up interrupts (continued) EXTI Acronym Description EXTI type Event Wake-up EXTI[14] EXTI line 14 from SYSCFG Configurable CPU1 and CPU2 EXTI[15] EXTI line 15 from SYSCFG Configurable CPU1 and CPU2 PVD line Configurable CPU1 and CPU2 RTC_ALARM...
- Page 510 Extended interrupts and event controller (EXTI) RM0453 Table 93. Wake-up interrupts (continued) EXTI Acronym Description EXTI type Event Wake-up Radio Busy RFBUSY wake-up Configurable CPU1 and CPU2 CDBGPWRUPREQ Debug power-up request wake-up Direct CPU1 and CPU2 1. For correct operation, the EXTI direct event EXTI_C2IMRm.IMb bit must be set to 0 before CPU1 uses this di- rect event.
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Page 511: Table 94. Exti Event Input Configurations And Register Control
RM0453 Extended interrupts and event controller (EXTI) Table 94. EXTI event input configurations and register control EXTI_ Event input EXTI_ EXTI_ EXTI_ EXTI_ EXTI_ Logic implementation CnEMR type RTSR FTSR SWIER CnIMR Configurable Configurable event input wake-up logic Direct Direct event input wake-up logic 1. -
Page 512: Table 95. Masking Functionality
Extended interrupts and event controller (EXTI) RM0453 Note: A detected configurable event interrupt pending request may be cleared by the CPU. The system is not able to enter into low-power modes as long as an interrupt pending request is active. 16.4.2 EXTI direct event input wake-up The extended interrupt/event block diagram for direct events is shown in... -
Page 513: Table 96. Exti Register Map Sections
RM0453 Extended interrupts and event controller (EXTI) Table 95. Masking functionality (continued) Configurable CPU interrupt enable CPU event enable CPUn event inputs it_exti_per(y) CPUn event EXTI_CnIMRm.IMb EXTI_CnEMRm.EMb wake-up EXTI_PRm.PIFb Status latched Masked Status latched 1. The single it_exti_per(y) interrupt goes to both CPUs. If no interrupt is required for the CPUn, the it_exti_per(y) interrupt must be masked in the CPUn NVIC. - Page 514 Extended interrupts and event controller (EXTI) RM0453 16.6.1 EXTI rising trigger selection register (EXTI_RTSR1) Address offset: 0x000 Reset value: 0x0000 0000 Contains only register bits for configurable events. Res. Res. Res. Res. Res. Res. Res. Res. Res. RT22 RT21 Res. Res.
- Page 515 RM0453 Extended interrupts and event controller (EXTI) 16.6.2 EXTI falling trigger selection register (EXTI_FTSR1) Address offset: 0x004 Reset value: 0x0000 0000 Contains only register bits for configurable events. Res. Res. Res. Res. Res. Res. Res. Res. Res. FT22 FT21 Res. Res.
- Page 516 Extended interrupts and event controller (EXTI) RM0453 16.6.3 EXTI software interrupt event register (EXTI_SWIER1) Address offset: 0x008 Reset value: 0x0000 0000 Contains only register bits for configurable events. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWI22 SWI21 Res. Res.
- Page 517 RM0453 Extended interrupts and event controller (EXTI) 16.6.4 EXTI pending register (EXTI_PR1) Address offset: 0x00C Reset value: 0x0000 0000 Contains only register bits for configurable events. Res. Res. Res. Res. Res. Res. Res. Res. Res. PIF22 PIF21 Res. Res. Res. Res.
- Page 518 Extended interrupts and event controller (EXTI) RM0453 16.6.5 EXTI rising trigger selection register (EXTI_RTSR2) Address offset: 0x020 Reset value: 0x0000 0000 Contains only register bits for configurable events. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 519 RM0453 Extended interrupts and event controller (EXTI) Bits 31:14 Reserved, must be kept at reset value. Bit 13 FT45: falling trigger event configuration bit of configurable event input 45 0: Falling trigger disabled (for event and interrupt) for input line 1: Falling trigger enabled (for event and interrupt) for input line Note: The configurable event inputs are edge triggered.
- Page 520 Extended interrupts and event controller (EXTI) RM0453 16.6.8 EXTI pending register (EXTI_PR2) Address offset: 0x02C Reset value: 0x0000 0000 Contains only register bits for configurable events. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 521 RM0453 Extended interrupts and event controller (EXTI) 16.6.10 EXTI event mask register (EXTI_CnEMR1) Address offset: Block 1: 0x084 Address offset: Block 2: 0x0C4 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. EM22 EM21 EM20 EM19 EM18 EM17 Res.
- Page 522 Extended interrupts and event controller (EXTI) RM0453 16.6.11 EXTI interrupt mask register (EXTI_CnIMR2) Address offset: Block 1: 0x090 Address offset: Block 2: 0x0D0 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
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Page 523: Table 97. Exti Register Map And Reset Values
RM0453 Extended interrupts and event controller (EXTI) Bits 31:10 Reserved, must be kept at reset value. Bit 9 EM41: Wake-up with event generation mask on event input 41 0: Event request from line 41 is masked. 1: Event request from line 41 is unmasked. Bit 8 EM40: Wake-up with event generation mask on event input 40 Bits 7:0 Reserved, must be kept at reset value. - Page 524 Extended interrupts and event controller (EXTI) RM0453 Table 97. EXTI register map and reset values (continued) Offset Register name EXTI_C2IMR1 0x0C0 Reset value EXTI_C2EMR1 0x0C4 Reset value 0x0C8 Reserved Reserved. EXTI_C2IMR2 0x0D0 Reset value EXTI_C2EMR2 0x0D4 Reset value Refer to Section 2.6 for the register boundary addresses.
- Page 525 RM0453 Cyclic redundancy check calculation unit (CRC) Cyclic redundancy check calculation unit (CRC) 17.1 Introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
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Page 526: Table 98. Crc Internal Input/Output Signals
Cyclic redundancy check calculation unit (CRC) RM0453 17.3 CRC functional description 17.3.1 CRC block diagram Figure 57. CRC calculation unit block diagram 32-bit AHB bus read access write access 32-bit accesses Data register Data register crc_hclk (output) (input) CRC_INIT CRC_CR CRC computation CRC_POL CRC_IDR... - Page 527 RM0453 Cyclic redundancy check calculation unit (CRC) The data size can be dynamically adjusted to minimize the number of write accesses for a given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write followed by a byte write.
- Page 528 Cyclic redundancy check calculation unit (CRC) RM0453 17.4 CRC registers The CRC_DR register can be accessed by words, right-aligned half-words and right-aligned bytes. For the other registers only 32-bit accesses are allowed. 17.4.1 CRC data register (CRC_DR) Address offset: 0x00 Reset value: 0xFFFF FFFF DR[31:16] DR[15:0]...
- Page 529 RM0453 Cyclic redundancy check calculation unit (CRC) 17.4.3 CRC control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. REV_ Res. Res. Res. Res. Res.
- Page 530 Cyclic redundancy check calculation unit (CRC) RM0453 17.4.4 CRC initial value (CRC_INIT) Address offset: 0x10 Reset value: 0xFFFF FFFF CRC_INIT[31:16] CRC_INIT[15:0] Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value This register is used to write the CRC initial value. 17.4.5 CRC polynomial (CRC_POL) Address offset: 0x14 Reset value: 0x04C1 1DB7 POL[31:16]...
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Page 531: Table 99. Crc Register Map And Reset Values
RM0453 Cyclic redundancy check calculation unit (CRC) 17.4.6 CRC register map Table 99. CRC register map and reset values Register Offset name CRC_DR DR[31:0] 0x00 Reset value CRC_IDR IDR[31:0] 0x04 Reset value CRC_CR 0x08 Reset value CRC_INIT CRC_INIT[31:0] 0x10 Reset value CRC_POL POL[31:0] 0x14... - Page 532 Analog-to-digital converter (ADC) RM0453 Analog-to-digital converter (ADC) 18.1 Introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18 multiplexed channels allowing it to measure signals from 12 external and 4 internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode.
- Page 533 RM0453 Analog-to-digital converter (ADC) 18.2 ADC main features • High performance – 12-bit, 10-bit, 8-bit or 6-bit configurable resolution – ADC conversion time: 0.4 µs for 12-bit resolution (2.5Msps), faster conversion times can be obtained by lowering resolution. – Self-calibration –...
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Page 534: Table 100. Adc Input/Output Pins
Analog-to-digital converter (ADC) RM0453 18.3 ADC functional description Figure 58 shows the ADC block diagram and Table 100 gives the ADC pin description. Figure 58. ADC block diagram Analog supply VREF+ 1.62 to 3.6 V AREADY SCANDIR EOSMP ADC interrupt IRQ up/down EOSEQ AUTOFF... -
Page 535: Table 101. Adc Internal Input/Output Signals
RM0453 Analog-to-digital converter (ADC) Table 101. ADC internal input/output signals Internal signal Signal type Description name Analog Input Connected either to internal channels or to ADC_INi channels external channels TRGx Input ADC conversion triggers Input Internal temperature sensor output voltage Input Internal voltage reference output voltage REFINT... - Page 536 Analog-to-digital converter (ADC) RM0453 regulator of the power control unit operates in normal Run mode (refer to Reset and clock control and power control sections). If the main voltage regulator enters low-power mode (such as Low-power run mode), this buffer is disabled and the ADC cannot be used. ADC Voltage regulator enable sequence To enable the ADC voltage regulator, set ADVREGEN bit to 1 in ADC_CR register.
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Page 537: Figure 59. Adc Calibration
RM0453 Analog-to-digital converter (ADC) Software calibration procedure Ensure that ADEN = 0, AUTOFF = 0, ADVREGEN = 1 and DMAEN = 0. Set ADCAL = 1. Wait until ADCAL = 0 (or until EOCAL = 1). This can be handled by interrupt if the interrupt is enabled by setting the EOCALIE bit in the ADC_IER register The calibration factor can be read from bits 6:0 of ADC_DR or ADC_CALFACT registers. -
Page 538: Figure 61. Enabling/Disabling The Adc
Analog-to-digital converter (ADC) RM0453 Two control bits are used to enable or disable the ADC: • Set ADEN = 1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready for operation. • Set ADDIS = 1 to disable the ADC and put the ADC in power down mode. The ADEN and ADDIS bits are then automatically cleared by hardware as soon as the ADC is fully disabled. -
Page 539: Figure 62. Adc Clock Scheme
RM0453 Analog-to-digital converter (ADC) 18.3.5 ADC clock (CKMODE, PRESC[3:0]) The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock (ADC asynchronous clock) independent from the APB clock (PCLK). Figure 62. ADC clock scheme ADITF (Reset &... -
Page 540: Table 103. Latency Between Trigger And Start Of Conversion
Analog-to-digital converter (ADC) RM0453 Table 103. Latency between trigger and start of conversion Latency between the trigger event ADC clock source CKMODE[1:0] and the start of conversion HSI16, SYSCLK or Latency is not deterministic (jitter) PLLPCLK Latency is deterministic (no jitter) and equal to PCLK divided by 2 3.25 ADC clock cycles Latency is deterministic (no jitter) and equal to... -
Page 541: Figure 63. Adc Connectivity
RM0453 Analog-to-digital converter (ADC) 18.3.6 ADC connectivity ADC inputs are connected to the external channels as well as internal sources as described Figure Figure 63. ADC connectivity STM32WLxx Channel selection ADC_IN0 ADC_IN1 ADC_IN2 ADC_IN3 ADC_IN4 ADC_IN5 ADC_IN6 REF+ ADC_IN7 ADC_IN8 ADC_IN9 [10] ADC_IN10... - Page 542 Analog-to-digital converter (ADC) RM0453 18.3.7 Configuring the ADC The software must write the ADCAL and ADEN bits in the ADC_CR register and configure the ADC_CFGR1 and ADC_CFGR2 registers only when the ADC is disabled (ADEN must be cleared). The software must only write to the ADSTART and ADDIS bits in the ADC_CR register only if the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and ADDIS = 0).
- Page 543 RM0453 Analog-to-digital converter (ADC) – Any channel can belong to in these sequences • Sequencer fully configurable The CHSELRMOD bit is set in ADC_CFGR1 register. – Sequencer length is up to 8 channels – The order in which the channels are scanned is independent from the channel number.
- Page 544 Analog-to-digital converter (ADC) RM0453 18.3.10 Single conversion mode (CONT In Single conversion mode, the ADC performs a single sequence of conversions, converting all the channels once. This mode is selected when CONT = 0 in the ADC_CFGR1 register. Conversion is started by either: •...
- Page 545 RM0453 Analog-to-digital converter (ADC) 18.3.12 Starting conversions (ADSTART) Software starts ADC conversions by setting ADSTART = 1. When ADSTART is set, the conversion: • Starts immediately if EXTEN = 00 (software trigger) • At the next active edge of the selected hardware trigger if EXTEN ≠ 00 The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing.
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Page 546: Figure 64. Analog To Digital Conversion Time
Analog-to-digital converter (ADC) RM0453 18.3.13 Timings The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution: = [1.5 + 12.5 ] x t CONV SMPL... -
Page 547: Table 104. Configuring The Trigger Polarity
RM0453 Analog-to-digital converter (ADC) 18.3.14 Stopping an ongoing conversion (ADSTP) The software can decide to stop any ongoing conversions by setting ADSTP = 1 in the ADC_CR register. This resets the ADC operation and the ADC is idle, ready for a new operation. When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is discarded (ADC_DR register is not updated with the current conversion). - Page 548 Analog-to-digital converter (ADC) RM0453 Refer to Table 102: External triggers Section 18.3.1: ADC pins and internal signals for the list of all the external triggers that can be used for regular conversion. The software source trigger events can be generated by setting the ADSTART bit in the ADC_CR register.
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Page 549: Table 105. Tsar Timings Depending On Resolution
RM0453 Analog-to-digital converter (ADC) Table 105. t timings depending on resolution CONV SMPL (min) RES[1:0] (ns) at (ns) at CONV (ADC clock cycles) (ADC clock (ADC clock bits = 35 MHz = 35 MHz cycles) cycles) (with min. t SMPL 12.5 10.5 18.4.3... -
Page 550: Figure 67. Single Conversions Of A Sequence, Software Trigger
Analog-to-digital converter (ADC) RM0453 18.4.5 Example timing diagrams (single/continuous modes hardware/software triggers) Figure 67. Single conversions of a sequence, software trigger ADSTART SCANDIR ADC state CH10 CH17 CH17 CH10 ADC_DR by S/W by H/W MSv30338V3 1. EXTEN = 00, CONT = 0 2. -
Page 551: Figure 69. Single Conversions Of A Sequence, Hardware Trigger
RM0453 Analog-to-digital converter (ADC) Figure 69. Single conversions of a sequence, hardware trigger ADSTART TRGx ADC state ADC_DR by S/W by H/W triggered ignored MSv30340V2 1. EXTSEL = TRGx (over-frequency), EXTEN = 01 (rising edge), CONT = 0 2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0 Figure 70. -
Page 552: Figure 71. Data Alignment And Resolution (Oversampling Disabled: Ovse = 0)
Analog-to-digital converter (ADC) RM0453 18.4.6 Low frequency trigger mode Once the ADC is enabled or the last ADC conversion is complete, the ADC is ready to start a new conversion. The ADC needs to be started at a predefined time (t ) otherwise ADC idle converted data might be corrupted due to the transistor leakage (refer to the device... -
Page 553: Figure 72. Example Of Overrun (Ovr)
RM0453 Analog-to-digital converter (ADC) When an overrun condition occurs, the ADC keeps operating and can continue to convert unless the software decides to stop and reset the sequence by setting the ADSTP bit in the ADC_CR register. The OVR flag is cleared by software by writing 1 to it. It is possible to configure if the data is preserved or overwritten when an overrun event occurs by programming the OVRMOD bit in the ADC_CFGR1 register: •... - Page 554 Analog-to-digital converter (ADC) RM0453 18.5.3 Managing a sequence of data converted without using the DMA If the conversions are slow enough, the conversion sequence can be handled by software. In this case the software must use the EOC flag and its associated interrupt to handle each data result.
- Page 555 RM0453 Analog-to-digital converter (ADC) When the DMA transfer is complete (all the transfers configured in the DMA controller have been done): • The content of the ADC data register is frozen. • Any ongoing conversion is aborted and its partial result discarded •...
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Page 556: Figure 73. Wait Mode Conversion (Continuous Mode, Software Trigger)
Analog-to-digital converter (ADC) RM0453 Figure 73. Wait mode conversion (continuous mode, software trigger) ADSTART ADSTP ADC_DR Read access STOP ADC state ADC_DR by H/W by S/W MSv30344V2 1. EXTEN = 00, CONT = 1 2. CHSEL = 0x3, SCANDIR = 0, WAIT = 1, AUTOFF = 0 18.6.2 Auto-off mode (AUTOFF) The ADC has an automatic power management feature which is called auto-off mode, and... -
Page 557: Figure 74. Behavior With Wait = 0, Autoff = 1
RM0453 Analog-to-digital converter (ADC) Figure 74. Behavior with WAIT = 0, AUTOFF = 1 TRGx ADC_DR Read access Startup Startup ADC state ADC_DR by S/W by H/W triggered MSv30345V2 1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1, AUTOFF = 1 Figure 75. -
Page 558: Table 106. Analog Watchdog Comparison
Analog-to-digital converter (ADC) RM0453 18.7.1 Description of analog watchdog 1 AWD1 analog watchdog is enabled by setting the AWD1EN bit in the ADC_CFGR1 register. It is used to monitor that either one selected channel or all enabled channels (see Table 107: Analog watchdog 1 channel selection) remain within a configured voltage range (window) as shown in... - Page 559 RM0453 Analog-to-digital converter (ADC) Table 107. Analog watchdog 1 channel selection (continued) Channels guarded by the analog watchdog AWD1SGL bit AWD1EN bit All channels Single channel 1. Selected by the AWD1CH[4:0] bits 18.7.2 Description of analog watchdog 2 and 3 The second and third analog watchdogs are more flexible and can guard several selected channels by programming the AWDxCHy in ADC_AWDxCR (x = 2, 3).
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Page 560: Figure 77. Adc_Awdx_Out Signal Generation
Analog-to-digital converter (ADC) RM0453 The AWD comparison is performed at the end of each ADC conversion. The ADC_AWDx_OUT rising edge and falling edge occurs two ADC_CLK clock cycles after the comparison. As ADC_AWDx_OUT is generated by the ADC_CLK domain and AWD flag is generated by the APB clock domain, the rising edges of these signals are not synchronized. -
Page 561: Figure 79. Adc_Awdx_Out Signal Generation (On A Single Channel)
RM0453 Analog-to-digital converter (ADC) Figure 79. ADC_AWDx_OUT signal generation (on a single channel) ADC STATE Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2 outside inside outside outside EOC FLAG EOS FLAG Cleared Cleared by SW by SW AWDx FLAG ADCy_AWDx_OUT - Converted channels: 1 and 2 - Only channel 1 is guarded MSv45364V1... -
Page 562: Figure 81. 20-Bit To 16-Bit Result Truncation
Analog-to-digital converter (ADC) RM0453 18.8 Oversampler The oversampling unit performs data preprocessing to offload the CPU. It can handle multiple conversions and average them into a single data with increased data width, up to 16-bit. It provides a result with the following form, where N and M can be adjusted: –... -
Page 563: Table 108. Maximum Output Results Vs N And M. Grayed Values Indicates Truncation
RM0453 Analog-to-digital converter (ADC) Figure 82. Numerical example with 5-bits shift and rounding Raw 20-bit data: Final result after 5-bits shift and rounding to nearest MS31929V1 Table 108 below gives the data format for the various N and M combination, for a raw conversion data equal to 0xFFF. - Page 564 Analog-to-digital converter (ADC) RM0453 18.8.1 ADC operating modes supported when oversampling In oversampling mode, most of the ADC operating modes are available: • Single or continuous mode conversions, forward or backward scanned sequences and up to 8 channels programmed sequence •...
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Page 565: Figure 83. Triggered Oversampling Mode (Tovs Bit = 1)
RM0453 Analog-to-digital converter (ADC) Figure 83. Triggered oversampling mode (TOVS bit = 1) Trigger Trigger CONT = 0 Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) (DISCEN = 1)* TOVS = 0 EOC flag set Trigger Trigger Trigger Trigger Trigger Trigger Trigger CONT = 0... -
Page 566: Figure 84. Temperature Sensor And Vrefint Channel Block Diagram
Analog-to-digital converter (ADC) RM0453 Main features • Linearity: ±2 °C max., precision depending on calibration Figure 84. Temperature sensor and V channel block diagram REFINT TSEN control bit Temperature sensor ADC V [12] converted data VREFEN control bit REFINT ADC V [13] Internal power block... - Page 567 RM0453 Analog-to-digital converter (ADC) Calculating the actual V voltage using the internal reference voltage REF+ voltage may be subject to variation or not precisely known. The embedded internal REF+ reference voltage (V ) and its calibration data acquired by the ADC during the REFINT manufacturing process at V can be used to evaluate the actual V...
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Page 568: Table 109. Adc Interrupts
Analog-to-digital converter (ADC) RM0453 the correct operation of the ADC, the VBAT pin is internally connected to a bridge divider. This bridge is automatically enabled when VBATEN is set, to connect V to the ADC [14] input channel. As a consequence, the converted digital value is V /3. - Page 569 RM0453 Analog-to-digital converter (ADC) Table 109. ADC interrupts (continued) Interrupt event Event flag Enable control bit Analog watchdog 2 status bit is set AWD2 AWD2IE Analog watchdog 3 status bit is set AWD3 AWD3IE Channel Configuration Ready CCRDY CCRDYIE End of sampling phase EOSMP EOSMPIE Overrun...
- Page 570 Analog-to-digital converter (ADC) RM0453 18.12 ADC registers Refer to Section 1.2 for a list of abbreviations used in register descriptions. 18.12.1 ADC interrupt and status register (ADC_ISR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res.
- Page 571 RM0453 Analog-to-digital converter (ADC) Bit 7 AWD1: Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1. 0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) 1: Analog watchdog event occurred...
- Page 572 Analog-to-digital converter (ADC) RM0453 18.12.2 ADC interrupt enable register (ADC_IER) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CCRD EOCAL AWD3I AWD2I AWD1I EOSMP ADRDY Res.
- Page 573 RM0453 Analog-to-digital converter (ADC) Bit 4 OVRIE: Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. 0: Overrun interrupt disabled 1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).
- Page 574 Analog-to-digital converter (ADC) RM0453 18.12.3 ADC control register (ADC_CR) Address offset: 0x08 Reset value: 0x0000 0000 ADVR ADCAL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EGEN ADSTA Res. Res. Res. Res. Res. Res. Res.
- Page 575 RM0453 Analog-to-digital converter (ADC) Bit 2 ADSTART: ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration).
- Page 576 Analog-to-digital converter (ADC) RM0453 18.12.4 ADC configuration register 1 (ADC_CFGR1) Address offset: 0x0C Reset value: 0x0000 0000 The software is allowed to program ADC_CFGR1 only when ADEN is cleared in ADC_CR. AWD1E AWD1S CHSEL DISCE Res. AWD1CH[4:0] Res. Res. Res. Res.
- Page 577 RM0453 Analog-to-digital converter (ADC) Bit 16 DISCEN: Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. 0: Discontinuous mode disabled 1: Discontinuous mode enabled Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.
- Page 578 Analog-to-digital converter (ADC) RM0453 Bits 8:6 EXTSEL[2:0]: External trigger selection These bits select the external event used to trigger the start of conversion (refer to Table 102: External triggers for details): 000: TRG0 001: TRG1 010: TRG2 011: TRG3 100: TRG4 101: TRG5 110: TRG6 111: TRG7...
- Page 579 RM0453 Analog-to-digital converter (ADC) 18.12.5 ADC configuration register 2 (ADC_CFGR2) Address offset: 0x10 Reset value: 0x0000 0000 The software is allowed to program ADC_CFGR2 only when ADEN is cleared in ADC_CR. CKMODE[1:0] LFTRIG Res. Res. Res. Res. Res. Res. Res. Res.
- Page 580 Analog-to-digital converter (ADC) RM0453 Bits 8:5 OVSS[3:0]: Oversampling shift This bit is set and cleared by software. 0000: No shift 0001: Shift 1-bit 0010: Shift 2-bits 0011: Shift 3-bits 0100: Shift 4-bits 0101: Shift 5-bits 0110: Shift 6-bits 0111: Shift 7-bits 1000: Shift 8-bits Others: Reserved Note: The software is allowed to write this bit only when ADEN bit is cleared.
- Page 581 RM0453 Analog-to-digital converter (ADC) Bits 31:26 Reserved, must be kept at reset value. Bits 25:8 SMPSELx: Channel-x sampling time selection (x = 17 to 0) These bits are written by software to define which sampling time is used. 0: Sampling time of CHANNELx use the setting of SMP1[2:0] register. 1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
- Page 582 Analog-to-digital converter (ADC) RM0453 Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to Section 18.7: Analog window watchdogs on page 557.
- Page 583 RM0453 Analog-to-digital converter (ADC) 18.12.9 ADC channel selection register (ADC_CHSELR) Address offset: 0x28 Reset value: 0x0000 0000 The same register can be used in two different modes: – Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to the current section.
- Page 584 Analog-to-digital converter (ADC) RM0453 18.12.10 ADC channel selection register [alternate] (ADC_CHSELR) Address offset: 0x28 Reset value: 0x0000 0000 The same register can be used in two different modes: – Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to the current previous section.
- Page 585 RM0453 Analog-to-digital converter (ADC) Bits 19:16 SQ5[3:0]: 5th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.
- Page 586 Analog-to-digital converter (ADC) RM0453 18.12.11 ADC watchdog threshold register (ADC_AWD3TR) Address offset: 0x2C Reset value: 0x0FFF 0000 Res. Res. Res. Res. HT3[11:0] Res. Res. Res. Res. LT3[11:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 HT3[11:0]: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog.
- Page 587 RM0453 Analog-to-digital converter (ADC) 18.12.13 ADC analog watchdog 2 configuration register (ADC_AWD2CR) Address offset: 0xA0 Reset value: 0x0000 0000 AWD2 AWD2 AWD2 AWD2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CH19R CH18R CH17 CH16 AWD2 AWD2 AWD2 AWD2...
- Page 588 Analog-to-digital converter (ADC) RM0453 18.12.15 ADC calibration factor (ADC_CALFACT) Address offset: 0xB4 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
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Page 589: Table 110. Adc Register Map And Reset Values
RM0453 Analog-to-digital converter (ADC) Bits 31:25 Reserved, must be kept at reset value. Bit 24 VBATEN: V enable This bit is set and cleared by software to enable/disable the V channel. 0: V channel disabled 1: V channel enabled Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing) Bit 23 TSEN: Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. - Page 590 Analog-to-digital converter (ADC) RM0453 Table 110. ADC register map and reset values (continued) Register Offset name ADC_IER 0x04 Reset value ADC_CR 0x08 Reset value EXTSEL ADC_CFGR1 AWDCH[4:0] [2:0] [1:0] 0x0C Reset value ADC_CFGR2 0x10 Reset value SMP2 SMP1 ADC_SMPR 0x14 [2:0] [2:0] Reset value...
- Page 591 RM0453 Analog-to-digital converter (ADC) Table 110. ADC register map and reset values (continued) Register Offset name ADC_AWD3CR 0xA4 Reset value Reserved Reserved ADC_CALFACT CALFACT[6:0] 0xB4 Reset value Reserved Reserved ADC_CCR 0x308 Reset value Refer to Section 2.6 for the register boundary addresses. RM0453 Rev 5 591/1450...
- Page 592 Digital-to-analog converter (DAC) RM0453 Digital-to-analog converter (DAC) 19.1 Introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data can be left- or right-aligned. The DAC features one single channel. An input reference pin, V (shared with others analog peripherals) is available for better REF+...
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Page 593: Table 111. Dac Features
RM0453 Digital-to-analog converter (DAC) 19.3 DAC implementation Table 111. DAC features DAC features Dual channel Output buffer I/O connection DAC_OUT1 to PA10 Maximum sampling time 1 Msps Autonomous mode VREF+ pin 19.4 DAC functional description 19.4.1 DAC block diagram Figure 86. DAC block diagram Offset calibration dac_ch1_trg1... -
Page 594: Table 112. Dac Input/Output Pins
Digital-to-analog converter (DAC) RM0453 19.4.2 DAC pins and internal signals The DAC includes: • One output channel • The DACx_OUT1 can be disconnected from the output pin and used as an ordinary GPIO • The dac_out1 can use an internal pin connection to on-chip peripherals such as comparator, operational amplifier and ADC (if available). -
Page 595: Figure 87. Data Registers In Single Dac Channel Mode
RM0453 Digital-to-analog converter (DAC) Table 114. DAC interconnection (continued) Signal name Source Source type Internal signal from on-chip dac_ch1_trg2 tim2_trgo timers TIM2_TGO_CKTIM Internal signal from on-chip dac_ch1_trg11 lptim1_out timers LPTIM1_OUT Internal signal from on-chip dac_ch1_trg12 lptim2_out timers LPTIM2_OUT Internal signal from on-chip dac_ch1_trg13 lptim3_out timers LPTIM3_OUT... -
Page 596: Figure 88. Timing Diagram For Conversion With Trigger Disabled Ten = 0
Digital-to-analog converter (DAC) RM0453 19.4.5 DAC conversion The DAC_DOR1 cannot be written directly and any data transfer to the DAC channel1 must be performed by loading the DAC_DHR1 register (write operation to DAC_DHR8R1, DAC_DHR12L1, DAC_DHR12R1). Data stored in the DAC_DHR1 register are automatically transferred to the DAC_DOR1 register after one dac_pclk clock cycle, if no hardware trigger is selected (TEN1 bit in DAC_CR register is reset). - Page 597 RM0453 Digital-to-analog converter (DAC) If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DOR1 register has been loaded with the DAC_DHR1 register contents. Note: TSEL1[3:0] bit cannot be changed when the EN1 bit is set. When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle.
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Page 598: Figure 89. Dac Lfsr Register Calculation Algorithm
Digital-to-analog converter (DAC) RM0453 Figure 89. DAC LFSR register calculation algorithm ai14713c The LFSR value, that may be masked partially or totally by means of the MAMP1[3:0] bits in the DAC_CR register, is added up to the DAC_DHR1 contents without overflow and this value is then transferred into the DAC_DOR1 register. -
Page 599: Figure 91. Dac Triangle Wave Generation
RM0453 Digital-to-analog converter (DAC) 19.4.10 Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVE1[1:0] to 10”. The amplitude is configured through the MAMP1[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three dac_pclk clock cycles after each trigger event. - Page 600 Digital-to-analog converter (DAC) RM0453 19.4.11 DAC channel modes The DAC channel can be configured in Normal mode or Sample and hold mode. The output buffer can be enabled to obtain a high drive capability. Before enabling output buffer, the voltage offset needs to be calibrated. This calibration is performed at the factory (loaded after reset) and can be adjusted by software during application operation.
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Page 601: Table 115. Sample And Refresh Timings
RM0453 Digital-to-analog converter (DAC) The timings for the three phases above are in units of LSI clock periods. As an example, to configure a sample time of 350 µs, a hold time of 2 ms and a refresh time of 100 µs assuming LSI ~32 KHz is selected: 12 cycles are required for sample phase: TSAMPLE1[9:0] = 11, 62 cycles are required for hold phase: THOLD1[9:0] = 62,... -
Page 602: Table 116. Channel Output Modes Summary
Digital-to-analog converter (DAC) RM0453 Figure 93. DAC Sample and hold mode phase diagram Sampling phase Hold phase Refresh Sampling phase dac_hold phase MSv45340V3 Like in Normal mode, the Sample and hold mode has different configurations. To enable the output buffer, MODE1[2:0] bits in DAC_MCR register must be set to: •... - Page 603 RM0453 Digital-to-analog converter (DAC) Table 116. Channel output modes summary (continued) MODE [2:0] Mode Buffer Output connections Connected to external pin Enabled Connected to external pin and to on chip peripherals (such as comparators) Sample and hold mode Connected to external pin and to on chip peripherals (such as comparators) Disabled Connected to on chip peripherals (such as comparators)
- Page 604 Digital-to-analog converter (DAC) RM0453 If the DAC channel is active, write 0 to EN1 bit in DAC_CR to disable the channel. Select a mode where the buffer is enabled, by writing to DAC_MCR register, MODE1[2:0] = 0b000 or 0b001 or 0b100 or 0b101. Start the DAC channel calibration, by setting the CEN1 bit in DAC_CR register to 1.
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Page 605: Table 117. Effect Of Low-Power Modes On Dac
RM0453 Digital-to-analog converter (DAC) Independent trigger with single LFSR generation To configure the DAC in this conversion mode, the following sequence is required: Set the DAC channel trigger enable bit, TEN1. Configure the trigger sources by setting different values in the TSEL1[3:0] bits. Configure the DAC channel WAVE1[1:0] bits as 01 and the same LFSR mask value in the MAMP1[3:0] bits. -
Page 606: Table 118. Dac Interrupts
Digital-to-analog converter (DAC) RM0453 Table 117. Effect of low-power modes on DAC (continued) Mode Description The DAC remains active with a static value if the Sample and hold mode is Stop 0 / Stop 1 selected using LSI clock. The DAC registers content is lost and must be reinitialized after exiting Stop 2 Stop 2. - Page 607 RM0453 Digital-to-analog converter (DAC) 19.7 DAC registers Refer to Section 1 on page 59 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 19.7.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res.
- Page 608 Digital-to-analog converter (DAC) RM0453 Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15...
- Page 609 RM0453 Digital-to-analog converter (DAC) 19.7.2 DAC software trigger register (DAC_SWTRGR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 610 Digital-to-analog converter (DAC) RM0453 19.7.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC1DHR[11:0] Res. Res. Res.
- Page 611 RM0453 Digital-to-analog converter (DAC) 19.7.6 DAC channel1 data output register (DAC_DOR1) Address offset: 0x2C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC1DOR[11:0] Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1.
- Page 612 Digital-to-analog converter (DAC) RM0453 Bit 12 Reserved, must be kept at reset value. Bit 11 Reserved, must be kept at reset value. Bits 10:0 Reserved, must be kept at reset value. 19.7.8 DAC calibration control register (DAC_CCR) Address offset: 0x38 Reset value: 0x0000 00XX Res.
- Page 613 RM0453 Digital-to-analog converter (DAC) Bit 8 Reserved, must be kept at reset value. Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 MODE1[2:0]: DAC channel1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1 = 0 and bit CEN1 = 0 in the DAC_CR register).
- Page 614 Digital-to-analog converter (DAC) RM0453 19.7.11 DAC sample and hold time register (DAC_SHHR) Address offset: 0x48 Reset value: 0x0001 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
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Page 615: Table 119. Dac Register Map And Reset Values
RM0453 Digital-to-analog converter (DAC) 19.7.13 DAC register map Table 119 summarizes the DAC registers. Table 119. DAC register map and reset values Register Offset name reset value DAC_CR Res. TSEL1[3:1] 0x00 Reset value DAC_ SWTRGR 0x04 Reset value DAC_ DACC1DHR[11:0] DHR12R1 0x08 Reset value... - Page 616 Digital-to-analog converter (DAC) RM0453 Table 119. DAC register map and reset values (continued) Register Offset name reset value DAC_ TREFRESH1[7:0] SHRR 0x4C Reset value 0x50- Reserved Res. 0x54 Refer to Section 2.6 on page 71 for the register boundary addresses. 616/1450 RM0453 Rev 5...
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Page 617: Table 120. Vref Buffer Modes
RM0453 Voltage reference buffer (VREFBUF) Voltage reference buffer (VREFBUF) 20.1 Introduction The devices embed a voltage reference buffer which can be used as voltage reference for ADC, DAC and also as voltage reference for external components through the VREF+ pin.When the VREF+ pin is double-bonded with VDDA pin in a package, the voltage reference buffer is not available and must be kept disabled (refer to datasheet for packages pinout description). - Page 618 Voltage reference buffer (VREFBUF) RM0453 20.3 VREFBUF registers 20.3.1 VREFBUF control and status register (VREFBUF_CSR) Address offset: 0x00 Reset value: 0x0000 0002 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
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Page 619: Table 121. Vrefbuf Register Map And Reset Values
RM0453 Voltage reference buffer (VREFBUF) Bits 31:6 Reserved, must be kept at reset value. Bits 5:0 TRIM[5:0]: Trimming code These bits are automatically initialized after reset with the trimming value stored in the flash memory during the production test. Writing into these bits allows the tuning of the internal reference buffer voltage. - Page 620 Comparator (COMP) RM0453 Comparator (COMP) 21.1 COMP introduction The device embeds two ultra-low-power comparators (COMP1 and COMP2). These comparators can be used for a variety of functions including the following: • wake up from low-power mode triggered by an analog signal •...
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Page 621: Table 122. Comp1 Input Plus Assignment
RM0453 Comparator (COMP) 21.3 COMP functional description 21.3.1 COMP block diagram The block diagram of the comparators is shown in the figure below. Figure 94. Comparator block diagram COMPx_INPSEL GPIO alternate function COMPx_POL COMPx_INP COMPx_OUT COMPx_INP I/Os COMPx COMPx_INM COMPx_VALUE COMPx_ COMPx_INMESEL Wakeup EXTI... -
Page 622: Table 123. Comp1 Input Minus Assignment
Comparator (COMP) RM0453 Table 123. COMP1 input minus assignment COMP1_INM COMP1_INMSEL[2:0] COMP1_INMESEL[1:0] 1/4 V Not affected REFINT 1/2 V Not affected REFINT 3/4 V Not affected REFINT Not affected REFINT DAC channel1 Not affected Reserved Not affected Not affected PA10 PA11 PA15 Reserved... - Page 623 RM0453 Comparator (COMP) 21.3.3 COMP reset and clocks The COMP clock provided by the clock controller is synchronous with the APB2 clock. There is no clock enable control bit provided in the RCC controller. Reset and clock enable bits are common for COMP and SYSCFG. Note: Important: The polarity selection logic and the output redirection to the port works independently from the APB2 clock.
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Page 624: Figure 95. Window Mode
Comparator (COMP) RM0453 Figure 95. Window mode COMPx_INPSEL COMPx_INP COMPx_INP I/Os COMPx COMPx_INM COMPx_INMSEL COMPx_INMESEL COMPx_INM I/Os COMPx_INM I/Os Internal sources WINMODE COMPx_INPSEL COMPy_INP COMPy_INP I/Os COMPy COMPy_INM COMPy_INMSEL COMPy_INMESEL COMPy_INM I/Os COMPy_INM I/Os Internal sources MSv37667V1 21.3.6 Hysteresis The comparator includes a programmable hysteresis to avoid spurious output transitions in case of noisy signals. -
Page 625: Figure 97. Comparator Output Blanking
RM0453 Comparator (COMP) 21.3.7 Comparator output blanking function The purpose of the blanking function is to prevent the current regulation to trip upon short current spikes at the beginning of the PWM period (typically the recovery current in power switches anti parallel diodes). It uses a blanking window defined with a timer output compare signal. -
Page 626: Table 126. Comparator Behavior In The Low-Power Modes
Comparator (COMP) RM0453 21.4 COMP low-power modes Table 126. Comparator behavior in the low-power modes Mode Description No effect on the comparators Sleep Comparator interrupts cause the device to exit the Sleep mode. LPRun No effect No effect on the comparators LPSleep Comparator interrupts cause the device to exit the LPSleep mode. - Page 627 RM0453 Comparator (COMP) 21.6 COMP registers 21.6.1 COMP1 control and status register (COMP1_CSR) Address offset: 0x00 Reset value: 0x0000 0000 SCAL LOCK VALUE Res. Res. Res. INMESEL[1:0] Res. BRGEN Res. BLANKING[2:0] HYST[1:0] POLA Res. Res. Res. Res. Res. Res. INPSEL[1:0] INMSEL[2:0] PWRMODE[1:0] Res.
- Page 628 Comparator (COMP) RM0453 Bits 20:18 BLANKING[2:0]: COMP1 blanking source selection These bits select which timer output controls the COMP1 output blanking. 000: No blanking 001: TIM1 OC5 selected as blanking source 010: TIM2 OC3 selected as blanking source Others: reserved Bits 17:16 HYST[1:0]: COMP1 hysteresis selection These bits are set and cleared by software.
- Page 629 RM0453 Comparator (COMP) 21.6.2 COMP2 control and status register (COMP2_CSR) Address offset: 0x04 Reset value: 0x0000 0000 SCAL LOCK VALUE Res. Res. Res. INMESEL[1:0] Res. BRGEN Res. BLANKING[2:0] HYST[1:0] POLA Res. Res. Res. Res. Res. INPSEL[1:0] INMSEL[2:0] PWRMODE[1:0] Res. RITY MODE Bit 31 LOCK: locks the whole content of the register, COMP2_CSR[31:0] This bit is set by software and cleared by a hardware system reset.
- Page 630 Comparator (COMP) RM0453 Bits 20:18 BLANKING[2:0]: COMP2 blanking source selection These bits select which timer output controls the COMP2 output blanking. 000: No blanking 001: TIM1 OC5 selected as blanking source 010: TIM2 OC3 selected as blanking source Others: reserved Bits 17:16 HYST[1:0]: COMP2 hysteresis selection These bits are set and cleared by software.
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Page 631: Table 128. Comp Register Map And Reset Values
RM0453 Comparator (COMP) Bit 0 EN: COMP2 enable This bit is set and cleared by software. It switches COMP2 on. 0: COMP2 switched off 1: COMP2 switched on 21.6.3 COMP register map Table 128. COMP register map and reset values Offset Register name COMP1_CSR 0x00... - Page 632 True random number generator (RNG) RM0453 True random number generator (RNG) 22.1 Introduction The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component.
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Page 633: Table 129. Rng Internal Input/Output Signals
RM0453 True random number generator (RNG) 22.3 RNG functional description 22.3.1 RNG block diagram Figure 98 shows the RNG block diagram. Figure 98. RNG block diagram True RNG rng_it Conditioning logic Banked Registers CONDRST RNG_CR RNG_DR RNG_SR interface Fault detection Clock checker rng_hclk 1-bit... -
Page 634: Figure 99. Nist Sp800-90B Entropy Source Model
True random number generator (RNG) RM0453 conditioning algorithm, a health monitoring block and two interfaces that are used to interact with the entropy source: GetEntropy and HealthTest. Figure 99. NIST SP800-90B entropy source model Error Output message (GetEntropy) (HealthTest) Conditioning Heath (optional) tests... - Page 635 RM0453 True random number generator (RNG) Conditioning The conditioning component in the RNG is a deterministic function that increases the entropy rate of the resulting fixed-length bitstrings output (128-bit). The NIST SP800-90B target is full entropy on the output (128-bit). The times required between two random number generations, and between the RNG initialization and availability of first sample are described in Section 22.5: RNG processing...
- Page 636 True random number generator (RNG) RM0453 Health checks This component ensures that the entire entropy source (with its noise source) starts then operates as expected, obtaining assurance that failures are caught quickly and with a high probability and reliability. The RNG implements the following health check features in accordance with NIST SP800-90B.
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Page 637: Figure 100. Rng Initialization Overview
RM0453 True random number generator (RNG) 22.3.4 RNG initialization The RNG simplified state machine is pictured on Figure 100. After enabling the RNG (RNGEN = 1 in RNG_CR), the following chain of events occurs: The analog noise source is enabled, and by default the RNG waits 16 cycles of RNG clock cycles (before divider) before starting to sample the analog output and filling the 128-bit conditioning shift register. - Page 638 True random number generator (RNG) RM0453 Figure 100 also highlights a possible software reset sequence, implemented by: Writing bits RNGEN = 0 and CONDRST = 1 in the RNG_CR register with the same RNG configuration and a new CLKDIV if needed. Then writing RNGEN = 1 and CONDRST = 0 in the RNG_CR register.
- Page 639 RM0453 True random number generator (RNG) additional words can be read by the application (in this case the DRDY bit is still high). If one or both of the above conditions are false, the RNG_DR register must not be read. If an error occurred, the error recovery sequence described in Section 22.3.7 must be...
- Page 640 True random number generator (RNG) RM0453 Note: The clock error has no impact on generated random numbers that is the application can still read the RNG_DR register. CEIS is set only when CECS is set to 1 by RNG. Noise source error detection When a noise source (or seed) error occurs, the RNG stops generating random numbers and sets to 1 both SEIS and SECS bits to indicate that a seed error occurred.
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Page 641: Table 130. Rng Interrupt Requests
22.6.1 Introduction In order to assess the amount of entropy available from the RNG, STMicroelectronics has tested the peripheral using the German BSI AIS-31 statistical tests (T0 to T8), and NIST SP800-90B test suite. The results can be provided on demand or the customer can reproduce the tests. -
Page 642: Table 131. Rng Configurations
“STM32 microcontrollers random number generation validation using NIST statistical test suite” application note (AN4230) available from www.st.com. Contact STMicroelectronics if the above samples need to be retrieved for the product. 22.7 RNG registers The RNG is associated with a control register, a data register and a status register. - Page 643 RM0453 True random number generator (RNG) Bit 31 CONFIGLOCK: RNG Config lock 0: Writes to the RNG_HTCR and RNG_CR configuration bits [29:4] are allowed. 1: Writes to the RNG_HTCR and RNG_CR configuration bits [29:4] are ignored until the next RNG reset. This bitfield is set once: if this bit is set it can only be reset to 0 if RNG is reset.
- Page 644 True random number generator (RNG) RM0453 Bit 5 CED: Clock error detection 0: Clock error detection enabled 1: Clock error detection is disabled The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, that is to enable or disable CED, the RNG must be disabled. Writing this bit is taken into account only if the CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0.
- Page 645 RM0453 True random number generator (RNG) Bit 2 SECS: Seed error current status 0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 1: At least one of the following faulty sequences has been detected: –...
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Page 646: Table 132. Rng Register Map And Reset Map
True random number generator (RNG) RM0453 22.7.4 RNG health test control register (RNG_HTCR) Address offset: 0x010 Reset value: 0x0000 5A4E Writing in RNG_HTCR is taken into account only if the CONDRST bit is set, and the CONFIGLOCK bit is cleared in the RNG_CR. Writing to this register is ignored if CONFIGLOCK=1. - Page 647 RM0453 AES hardware accelerator (AES) AES hardware accelerator (AES) 23.1 Introduction The AES hardware accelerator (AES) encrypts or decrypts data, using an algorithm and implementation fully compliant with the advanced encryption standard (AES) defined in Federal information processing standards (FIPS) publication 197. The peripheral supports CTR, GCM, GMAC, CCM, ECB, and CBC chaining modes for key sizes of 128 or 256 bits.
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Page 648: Table 133. Aes Internal Input/Output Signals
AES hardware accelerator (AES) RM0453 23.3 AES implementation The devices have one AES peripheral. 23.4 AES functional description 23.4.1 AES block diagram Figure 101 shows the block diagram of AES. Figure 101. AES block diagram 32-bit Banked registers access AES_KEYRx 32-bit AHB bus AES_IVRx... - Page 649 RM0453 AES hardware accelerator (AES) 23.4.3 AES cryptographic core Overview The AES cryptographic core consists of the following components: • AES core algorithm (AEA) • multiplier over a binary Galois field (GF2mul) • key input • initialization vector (IV) input •...
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Page 650: Figure 102. Ecb Encryption And Decryption Principle
AES hardware accelerator (AES) RM0453 Note: The chaining mode may be changed only when AES is disabled (bit EN of the AES_CR register cleared). Principle of each AES chaining mode is provided in the following subsections. Detailed information is in dedicated sections, starting from Section 23.4.8: AES basic chaining modes (ECB, CBC). -
Page 651: Figure 103. Cbc Encryption And Decryption Principle
RM0453 AES hardware accelerator (AES) Cipher block chaining (CBC) mode Figure 103. CBC encryption and decryption principle Encryption Plaintext block 1 Plaintext block 2 Plaintext block 3 initialization vector Encrypt Encrypt Encrypt Ciphertext block 1 Ciphertext block 2 Ciphertext block 3 Decryption Plaintext block 1 Plaintext block 2... -
Page 652: Figure 104. Ctr Encryption And Decryption Principle
AES hardware accelerator (AES) RM0453 Counter (CTR) mode Figure 104. CTR encryption and decryption principle Encryption Counter Counter Counter value value + 1 value + 2 Encrypt Encrypt Encrypt Plaintext block 1 Plaintext block 2 Plaintext block 3 Ciphertext block 1 Ciphertext block 2 Ciphertext block 3 Decryption... -
Page 653: Figure 105. Gcm Encryption And Authentication Principle
RM0453 AES hardware accelerator (AES) Galois/counter mode (GCM) Figure 105. GCM encryption and authentication principle Initialization Counter Counter Counter vector value value + 1 value + 2 Init Encrypt Encrypt Encrypt (Encrypt) Plaintext block 1 Plaintext block 2 Plaintext block 3 Ciphertext block 1 Ciphertext block 2 Ciphertext block 3... -
Page 654: Figure 107. Ccm Encryption And Authentication Principle
AES hardware accelerator (AES) RM0453 GMAC is similar to GCM, except that it is applied on a message composed only by plaintext authenticated data (that is, only header, no payload). Counter with CBC-MAC (CCM) principle Figure 107. CCM encryption and authentication principle Count 1 Count 2 Count 3... - Page 655 RM0453 AES hardware accelerator (AES) Initialization of AES To initialize AES, first disable it by clearing the EN bit of the AES_CR register. Then perform the following steps in any order: • Configure the AES mode, by programming the MODE[1:0] bitfield of the AES_CR register.
- Page 656 AES hardware accelerator (AES) RM0453 Data append using interrupt The method uses interrupt from the AES peripheral to control the data append, through the following sequence: Enable interrupts from AES by setting the CCFIE bit of the AES_CR register. Enable the AES peripheral by setting the EN bit of the AES_CR register. Write first four input data words into the AES_DINR register.
- Page 657 RM0453 AES hardware accelerator (AES) 23.4.5 AES decryption round key preparation Internal key schedule is used to generate AES round keys. In AES encryption, the round 0 key is the one stored in the key registers. AES decryption must start using the last round key.
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Page 658: Figure 108. Example Of Suspend Mode Management
AES hardware accelerator (AES) RM0453 23.4.7 AES task suspend and resume A message can be suspended if another message with a higher priority must be processed. When this highest priority message is sent, the suspended message can resume in both encryption or decryption mode. -
Page 659: Figure 109. Ecb Encryption
RM0453 AES hardware accelerator (AES) Figure 109 illustrates the electronic codebook (ECB) encryption. Figure 109. ECB encryption Block 1 Block 2 AES_DINR (plaintext P1) AES_DINR (plaintext P2) Swap Swap DATATYPE[1:0] DATATYPE[1:0] management management AES_KEYRx (KEY) AES_KEYRx (KEY) Encrypt Encrypt Legend AES core Swap Swap... -
Page 660: Figure 111. Cbc Encryption
AES hardware accelerator (AES) RM0453 Figure 111 illustrates the cipher block chaining (CBC) encryption. Figure 111. CBC encryption Block 1 Block 2 AES_DINR (plaintext P1) AES_DINR (plaintext P2) Swap Swap DATATYPE[1:0] DATATYPE[1:0] management management AES_IVRx (init. vector) AES_KEYRx (KEY) AES_KEYRx (KEY) Block cipher Block cipher encryption... -
Page 661: Figure 113. Ecb/Cbc Encryption (Mode 1)
RM0453 AES hardware accelerator (AES) The second ciphertext block is processed in the same way as the first block, except that the I1 data from the first block is used in place of the initialization vector. The decryption continues in this way until the last complete ciphertext block is decrypted. If the message size is not a multiple of 128 bits, the final partial data block is decrypted in the way explained in Section 23.4.6: AES ciphertext stealing and data... -
Page 662: Figure 114. Ecb/Cbc Decryption (Mode 3)
AES hardware accelerator (AES) RM0453 register to 000 or 001, respectively. Data type can also be defined, using DATATYPE[1:0] bitfield. KEYSIZE bitfield must be kept as-is. Write the AES_IVRx registers with the initialization vector (required in CBC mode only). Enable AES by setting the EN bit of the AES_CR register. Write the AES_DINR register four times to input the cipher text (MSB first), as shown in Figure 114. -
Page 663: Figure 115. Message Construction In Ctr Mode
RM0453 AES hardware accelerator (AES) To resume the processing of a message, proceed as follows: If DMA is used, configure the DMA controller so as to complete the rest of the FIFO IN and FIFO OUT transfers. Disable the AES peripheral by clearing the EN bit of the AES_CR register. Restore AES_CR register (with correct KEYSIZE) then restore AES_KEYRx registers. -
Page 664: Table 134. Ctr Mode Initialization Vector Definition
AES hardware accelerator (AES) RM0453 CTR encryption and decryption Figure 116 Figure 117 describe the CTR encryption and decryption process, respectively, as implemented in the AES peripheral. The CTR mode is selected by writing 010 to the CHMOD[2:0] bitfield of AES_CR register. Figure 116. - Page 665 RM0453 AES hardware accelerator (AES) Unlike in CBC mode that uses the AES_IVRx registers only once when processing the first data block, in CTR mode AES_IVRx registers are used for processing each data block, and the AES peripheral increments the counter bits of the initialization vector (leaving the nonce bits unchanged).
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Page 666: Table 135. Gcm Last Block Definition
AES hardware accelerator (AES) RM0453 Figure 118. Message construction in GCM [Len(A)] [Len(C)] Len(A) Len(P) = Len(C) 16-byte boundaries Additional authenticated data Last Plaintext (P) (AAD) block 4-byte boundaries Authenticated & encrypted ciphertext (C) Initialization vector (IV) Counter Authentication tag (T) Zero padding / zeroed bits MSv42157V1 The message has the following structure:... -
Page 667: Table 136. Initialization Of Aes_Ivrx Registers In Gcm Mode
RM0453 AES hardware accelerator (AES) GCM processing Figure 119 describes the GCM implementation in the AES peripheral. The GCM is selected by writing 011 to the CHMOD[2:0] bitfield of the AES_CR register. Figure 119. GCM authenticated encryption (3) Payload Block 1 Block n AES_IVRx ICB + (32-bit counter = 0x02) - Page 668 AES hardware accelerator (AES) RM0453 The authentication mechanism in GCM mode is based on a hash function called GF2mul that performs multiplication by a fixed parameter, called hash subkey (H), within a binary Galois field. A GCM message is processed through the following phases, further described in next subsections: •...
- Page 669 RM0453 AES hardware accelerator (AES) GCM payload phase This phase, identical for encryption and decryption, is executed after the GCM header phase. During this phase, the encrypted/decrypted payload is stored in the AES_DOUTR register. The sequence to execute is: Indicate the payload phase, by setting to 10 the GCMPH[1:0] bitfield of the AES_CR register.
- Page 670 AES hardware accelerator (AES) RM0453 Suspend/resume operations in GCM mode To suspend the processing of a message, proceed as follows: If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN bit of the AES_CR register. If DMA is not used, make sure that the current computation is completed, which is indicated by the CCF flag of the AES_SR register set to 1.
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Page 671: Figure 120. Message Construction In Gmac Mode
RM0453 AES hardware accelerator (AES) A typical message construction for GMAC is given in Figure 120. Figure 120. Message construction in GMAC mode [Len(A)] Len(A) 16-byte boundaries Last Authenticated data block 4-byte boundaries Authentication tag (T) Initialization vector (IV) Counter Zero padding MSv42158V2 AES GMAC processing... -
Page 672: Figure 122. Message Construction In Ccm Mode
AES hardware accelerator (AES) RM0453 Suspend/resume operations in GMAC In GMAC mode, the sequence described for the GCM applies except that only the header phase can be interrupted. 23.4.12 AES counter with CBC-MAC (CCM) Overview The AES counter with cipher block chaining-message authentication code (CCM) algorithm allows encryption and authentication of plaintext, generating the corresponding ciphertext and tag (also known as message authentication code). - Page 673 RM0453 AES hardware accelerator (AES) known length Len(A) that can be a non-multiple of 16 bytes (see Figure 122). The standard also states that, on MSB bits of the first message block (B1), the associated data length expressed in bytes (a) must be encoded as follows: –...
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Page 674: Table 137. Initialization Of Aes_Ivrx Registers In Ccm Mode
AES hardware accelerator (AES) RM0453 CCM processing Figure 123 describes the CCM implementation within the AES peripheral (encryption example). This mode is selected by writing 100 into the CHMOD[2:0] bitfield of the AES_CR register. Figure 123. CCM mode authenticated encryption Block 1 Block m (3) Payload... - Page 675 RM0453 AES hardware accelerator (AES) Note: In this mode, the setting 01 of the MODE[1:0] bitfield (key derivation) is forbidden. A CCM message is processed through the following phases, further described in next subsections: • Init phase: AES processes the first block and prepares the first counter block. •...
- Page 676 AES hardware accelerator (AES) RM0453 CCM payload phase (encryption or decryption) This phase, identical for encryption and decryption, is executed after the CCM header phase. During this phase, the encrypted/decrypted payload is stored in the AES_DOUTR register. The sequence to execute is: Indicate the payload phase, by setting to 10 the GCMPH[1:0] bitfield of the AES_CR register.
- Page 677 RM0453 AES hardware accelerator (AES) AES_SR register then stop the DMA transfers from the OUT FIFO by clearing the DMAOUTEN bit of the AES_CR register. Clear the CCF flag of the AES_SR register, by setting to 1 the CCFC bit of the AES_CR register.
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Page 678: Figure 124. 128-Bit Block Construction With Respect To Data Swap
AES hardware accelerator (AES) RM0453 Data swapping The AES peripheral can be configured to perform a bit-, a byte-, a half-word-, or no swapping on the input data word in the AES_DINR register, before loading it to the AES processing core, and on the data output from the AES processing core, before sending it to the AES_DOUTR register. -
Page 679: Table 138. Key Endianness In Aes_Keyrx Registers (128- Or 256-Bit Key Length)
RM0453 AES hardware accelerator (AES) Note: The data in AES key registers (AES_KEYRx) and initialization registers (AES_IVRx) are not sensitive to the swap mode selection. Data padding Figure 124 also gives an example of memory data block padding with zeros such that the zeroed bits after the data swap form a contiguous zone at the MSB end of the AES core input buffer. -
Page 680: Figure 125. Dma Transfer Of A 128-Bit Data Block During Input Phase
AES hardware accelerator (AES) RM0453 23.4.16 AES DMA interface The AES peripheral provides an interface to connect to the DMA (direct memory access) controller. The DMA operation is controlled through the AES_CR register. Data input using DMA Setting the DMAINEN bit of the AES_CR register enables DMA writing into AES. The AES peripheral then initiates a DMA request during the input phase each time it requires to write a 128-bit block (quadruple word) to the AES_DINR register, as shown in Figure... -
Page 681: Figure 126. Dma Transfer Of A 128-Bit Data Block During Output Phase
RM0453 AES hardware accelerator (AES) Figure 126. DMA transfer of a 128-bit data block during output phase Chronological order Increasing address Memory accessed through DMA Word3 Word2 Word1 Word0 DOUT[127:96] DOUT[95:64] DOUT[63:32] DOUT[31:0] D127 DMA req N DMA req N+1 DMA req N+2 DMA req N+3 single read... -
Page 682: Table 139. Aes Interrupt Requests
AES hardware accelerator (AES) RM0453 Note: AES is not disabled after a WRERR error detection and continues processing. An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details, refer to Section 23.5: AES interrupts. -
Page 683: Table 141. Processing Latency For Gcm And Ccm (In Clock Cycles)
RM0453 AES hardware accelerator (AES) Table 141. Processing latency for GCM and CCM (in clock cycles) Header Payload Key size Mode of operation Algorithm Init Phase Tag phase phase phase Mode 1: Encryption/ 128-bit Mode 3: Decryption Mode 1: Encryption/ 256-bit Mode 3: Decryption 1. - Page 684 AES hardware accelerator (AES) RM0453 Bits 14:13 GCMPH[1:0]: GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: 00: Init phase 01: Header phase 10: Payload phase 11: Final phase The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield).
- Page 685 RM0453 AES hardware accelerator (AES) Bits 16, 6:5 CHMOD[2:0]: Chaining mode selection This bitfield selects the AES chaining mode: 000: Electronic codebook (ECB) 001: Cipher-block chaining (CBC) 010: Counter mode (CTR) 011: Galois counter mode (GCM) and Galois message authentication code (GMAC) 100: Counter with CBC-MAC (CCM) others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the...
- Page 686 AES hardware accelerator (AES) RM0453 Bit 3 BUSY: Busy This flag indicates whether AES is idle or busy during GCM payload encryption phase: 0: Idle 1: Busy When the flag indicates “idle”, the current GCM encryption processing may be suspended to process a higher-priority message.
- Page 687 RM0453 AES hardware accelerator (AES) 23.7.3 AES data input register (AES_DINR) Address offset: 0x08 Reset value: 0x0000 0000 Only 32-bit access type is supported. DIN[31:16] DIN[15:0] Bits 31:0 DIN[31:0]: Input data word A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the AES peripheral.
- Page 688 AES hardware accelerator (AES) RM0453 Bits 31:0 DOUT[31:0]: Output data word This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the AES peripheral.
- Page 689 RM0453 AES hardware accelerator (AES) Bits 31:0 KEY[63:32]: Cryptographic key, bits [63:32] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield. 23.7.7 AES key register 2 (AES_KEYR2) Address offset: 0x18 Reset value: 0x0000 0000 KEY[95:80] KEY[79:64] Bits 31:0 KEY[95:64]: Cryptographic key, bits [95:64] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
- Page 690 AES hardware accelerator (AES) RM0453 Bits 31:0 IVI[31:0]: Initialization vector input, bits [31:0] Refer to Section 23.4.15: AES initialization vector registers on page 679 for description of the IVI[127:0] bitfield. The initialization vector is only used in chaining modes other than ECB. The AES_IVRx registers may be written only when the AES peripheral is disabled 23.7.10 AES initialization vector register 1 (AES_IVR1)
- Page 691 RM0453 AES hardware accelerator (AES) Bits 31:0 IVI[127:96]: Initialization vector input, bits [127:96] Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield. 23.7.13 AES key register 4 (AES_KEYR4) Address offset: 0x30 Reset value: 0x0000 0000 KEY[159:144] KEY[143:128] Bits 31:0 KEY[159:128]: Cryptographic key, bits [159:128] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
- Page 692 AES hardware accelerator (AES) RM0453 23.7.16 AES key register 7 (AES_KEYR7) Address offset: 0x3C Reset value: 0x0000 0000 KEY[255:240] KEY[239:224] Bits 31:0 KEY[255:224]: Cryptographic key, bits [255:224] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield. Note: The key registers from 4 to 7 are used only when the key length of 256 bits is selected. They have no effect when the key length of 128 bits is selected (only key registers 0 to 3 are used in that case).
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Page 693: Table 142. Aes Register Map And Reset Values
RM0453 AES hardware accelerator (AES) 23.7.18 AES register map Table 142. AES register map and reset values Offset Register AES_CR 0x000 Reset value AES_SR 0x004 Reset value AES_DINR DIN[31:0] 0x008 Reset value AES_DOUTR DOUT[31:0] 0x00C Reset value AES_KEYR0 KEY[31:0] 0x010 Reset value AES_KEYR1 KEY[63:32]... - Page 694 AES hardware accelerator (AES) RM0453 Table 142. AES register map and reset values (continued) Offset Register AES_SUSP1R SUSP[31:0] 0x044 Reset value AES_SUSP2R SUSP[31:0] 0x048 Reset value AES_SUSP3R SUSP[31:0] 0x04C Reset value AES_SUSP4R SUSP[31:0] 0x050 Reset value AES_SUSP5R SUSP[31:0] 0x054 Reset value AES_SUSP6R SUSP[31:0] 0x058...
- Page 695 RM0453 Public key accelerator (PKA) Public key accelerator (PKA) 24.1 Introduction PKA (public key accelerator) is intended for the computation of cryptographic public key primitives, specifically those related to RSA, Diffie-Hellmann or ECC (elliptic curve cryptography) over GF(p) (Galois fields). To achieve high performance at a reasonable cost, these operations are executed in the Montgomery domain.
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Page 696: Table 143. Internal Input/Output Signals
Public key accelerator (PKA) RM0453 Figure 127. PKA block diagram PKA32 Banked registers (main) PKA_CR control PKA_SR status interface PKA_CLRFR clear 894x32-bit PKA RAM pka_hclk 32-bit Control PKA core pka_it interface logic MS45419V1 24.3.2 PKA internal signals Table 143 lists internal signals available at the IP level, not necessarily available on product bonding pads. -
Page 697: Table 144. Pka Integer Arithmetic Functions List
RM0453 Public key accelerator (PKA) PKA operating modes The list of operations the PKA can perform is detailed in Table 144 Table 145, respectively, for integer arithmetic functions and prime field (Fp) elliptic curve functions. Each of these operating modes has an associated code that has to be written to the MODE field in the PKA_CR register. - Page 698 Public key accelerator (PKA) RM0453 supplied before starting the operation. Performance improvement is detailed in Section 24.5.2: Computation times. The operations using fast mode are modular exponentiation and scalar multiplication. 24.3.5 Typical applications for PKA Introduction The PKA can be used to accelerate a number of public key cryptographic functions. In particular: •...
- Page 699 RM0453 Public key accelerator (PKA) Alice, to decrypt ciphertext c using her private key, follows the steps indicated below: Convert the ciphertext C to an integer ciphertext representative c. Recover plaintext m = c mod n = (m mod n. If the private key is the quintuple (p, q, dp, dq, qInv), then plaintext m is obtained by performing the operations: mod p mod q...
- Page 700 Public key accelerator (PKA) RM0453 ECDSA signature verification ECDSA (elliptic curve digital signature algorithm) signature verification function principle is the following: Bob, to authenticate Alice's signature, must have a copy of her public key curve point Q Bob can verify that Q is a valid curve point going through the following steps: check that Q is not equal to the identity element O...
- Page 701 RM0453 Public key accelerator (PKA) Using precomputed Montgomery parameters (PKA fast mode) As explained in Section 24.3.4, when computing many operations with the same modulus it can be beneficial for the application to compute only once the corresponding Montgomery parameter (see, for example, Section 24.4.5).
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Page 702: Table 146. Montgomery Parameter Computation
Public key accelerator (PKA) RM0453 Note: Fractional results for above formulas are rounded up to the nearest integer since PKA core processes 32-bit words. Note: The maximum ROS is 99 words (3136-bit max exponent size), while the maximum EOS is 21 words (640-bit max operand size). -
Page 703: Table 147. Modular Addition
RM0453 Public key accelerator (PKA) 24.4.3 Modular addition Modular addition operation consists in the computation of A + B mod n. Operation instructions are summarized in Table 147. Table 147. Modular addition Parameters with direction Value (Note) Storage Size MODE 0x0E PKA_CR 6 bits... -
Page 704: Table 149. Montgomery Multiplication
Public key accelerator (PKA) RM0453 Inward (or outward) conversion into (or from) Montgomery domain Let’s assume A is an integer in the natural domain Compute r2modn using Montgomery parameter computation Result AR= A x r2modn mod n is A in the Montgomery domain Let’s assume BR is an integer in the Montgomery domain Result B = BR x 1 mod n is B in the natural domain Similarly, above value AR computed in a) can be converted into the natural... -
Page 705: Table 150. Modular Exponentiation (Normal Mode)
RM0453 Public key accelerator (PKA) Table 150. Modular exponentiation (normal mode) Parameters with direction Value (Note) Storage Size MODE 0x00 PKA_CR 6 bits Exponent length (in bits, not null) RAM@0x400 32 bits Operand length (in bits, not null) RAM@0x404 Operand A (base of IN/OUT (0 ≤... -
Page 706: Table 153. Modular Reduction
Public key accelerator (PKA) RM0453 24.4.8 Modular reduction Modular reduction operation consists in the computation of the remainder of A divided by n. Operation instructions are summarized in Table 153. Table 153. Modular reduction Parameters with direction Value (Note) Storage Size MODE 0x0D... -
Page 707: Table 156. Arithmetic Multiplication
RM0453 Public key accelerator (PKA) 24.4.11 Arithmetic multiplication Arithmetic multiplication operation consists in the computation of AxB. Operation instructions are summarized in Table 156. Table 156. Arithmetic multiplication Parameters with direction Value (Note) Storage Size MODE 0x0B PKA_CR 6 bits Operand length M (In bits, not null) RAM@0x404... -
Page 708: Table 158. Crt Exponentiation
Public key accelerator (PKA) RM0453 These values allow the recipient to compute the exponentiation m = A (mod pq) more efficiently as follows: • mod p • mod p • h = q ) mod p, with m > m •... -
Page 709: Table 159. Point On Elliptic Curve Fp Check
RM0453 Public key accelerator (PKA) Table 159. Point on elliptic curve Fp check Parameters with direction Value (Note) Storage Size MODE 0x28 PKA_CR 6 bits (In bits, not null, Modulus length RAM@0x404 8 < value < 640) 32 bits 0x0: positive Curve coefficient a sign RAM@0x408 0x1: negative... -
Page 710: Table 161. Ecc Fp Scalar Multiplication (Fast Mode)
Public key accelerator (PKA) RM0453 Table 161. ECC Fp scalar multiplication (Fast Mode) Parameters with direction Value (Note) Storage Size MODE 0x22 PKA_CR 6 bits (In bits, not null, Scalar multiplier k length RAM@0x400 8 < value < 640) (In bits, not null, Modulus length RAM@0x404 32 bits... -
Page 711: Table 162. Ecdsa Sign - Inputs
RM0453 Public key accelerator (PKA) Table 162. ECDSA sign - Inputs Parameters with direction Value (Note) Storage Size MODE 0x24 PKA_CR 6 bits Curve prime order n (in bits, not null) RAM@0x400 length Curve modulus p length (in bits, 8 < value < 640) RAM@0x404 32 bits 0x0: positive... -
Page 712: Table 164. Extended Ecdsa Sign (Extra Outputs)
Public key accelerator (PKA) RM0453 Table 164. Extended ECDSA sign (extra outputs) Parameters with direction Value (Note) Storage Size Curve point kG coordinate x (0 ≤ x < p) RAM@0x103C Curve point kG coordinate y (0 ≤ y < p) RAM@0x1090 24.4.17 ECDSA verification... -
Page 713: Table 167. Family Of Supported Curves For Ecc Operations
RM0453 Public key accelerator (PKA) 24.5 Example of configurations and processing times 24.5.1 Supported elliptic curves The PKA supports all non-singular elliptic curves defined over prime fields. Those curvescan be described with a short Weierstrass equation y + ax + b (mod p). Note: Binary curves, Edwards curves and Curve25519 are not supported by the PKA. - Page 714 Public key accelerator (PKA) RM0453 Table 167. Family of supported curves for ECC operations (continued) Curve name Standard Reference brainpoolP224r1, brainpoolP224t1 brainpoolP256r1, brainpoolP256t1 – Brainpool Elliptic Curves, IETF RFC 5639 brainpoolP320r1, – Brainpool Elliptic Curves for the Internet Key IETF https://tools.ietf.org brainpoolP320t1 Exchange (IKE) Group Description Registry, IETF...
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Page 715: Table 168. Modular Exponentiation Computation Times
RM0453 Public key accelerator (PKA) 24.5.2 Computation times The following tables summarize the PKA computation times, expressed in clock cycles. Table 168. Modular exponentiation computation times Modulus length (in bits) Exponent length Mode (in bits) 1024 2048 3072 Normal 304000 814000 1728000 Fast... -
Page 716: Table 171. Ecdsa Verification Average Computation Times
Public key accelerator (PKA) RM0453 Table 171. ECDSA verification average computation times Modulus length (in bits) 3500000 5350000 10498000 18126000 29118000 61346000 71588000 Table 172. Point on elliptic curve Fp check average computation times Modulus length (in bits) 10800 14200 20400 31000 49600... - Page 717 RM0453 Public key accelerator (PKA) 24.7 PKA registers 24.7.1 PKA control register (PKA_CR) Address offset: 0x00 Reset value: 0x0000 0000 ADDR PROC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ERRIE ERRIE ENDIE Res. Res. MODE[5:0] Res.
- Page 718 Public key accelerator (PKA) RM0453 Bits 7:2 Reserved, must be kept at reset value. Bit 1 START: start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. Note: START is ignored if PKA is busy.
- Page 719 RM0453 Public key accelerator (PKA) 24.7.3 PKA clear flag register (PKA_CLRFR) Address offset: 0x08 Reset value: 0x0000 0000 ADDR PROC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ERRFC ERRFC ENDFC Res. Res. Res. Res. Res.
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Page 720: Table 175. Pka Register Map And Reset Values
Public key accelerator (PKA) RM0453 24.7.5 PKA register map Table 175. PKA register map and reset values Register Offset name PKA_CR MODE[5:0] 0x000 Reset value PKA_SR 0x004 Reset value PKA_CLRFR 0x008 Reset value Refer to Section 2.6 on page 71 for the register boundary addresses. - Page 721 RM0453 Advanced-control timer (TIM1) Advanced-control timer (TIM1) In this section, “TIMx” should be understood as “TIM1” since there is only one instance of this type of timer for the products to which this reference manual applies. 25.1 TIM1 introduction The advanced-control timer (TIM1) consists of a 16-bit auto-reload counter driven by a programmable prescaler.
- Page 722 Advanced-control timer (TIM1) RM0453 25.2 TIM1 main features TIM1 timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65536. •...
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Page 723: Figure 128. Advanced-Control Timer Block Diagram
RM0453 Advanced-control timer (TIM1) Figure 128. Advanced-control timer block diagram Internal clock (CK_INT) from RCC Trigger ETRF TRGO controller ETRP TIMx_ETR to other timers Polarity selection & Input to peripherals edgedetector & prescaler filter On-chip ETR ITR[0..15] sources Slave Reset, enable, up/down, count TRGI controller mode... - Page 724 Advanced-control timer (TIM1) RM0453 25.3 TIM1 functional description 25.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
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Page 725: Figure 129. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0453 Advanced-control timer (TIM1) Figure 129. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 130. - Page 726 Advanced-control timer (TIM1) RM0453 25.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1.
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Page 727: Figure 131. Counter Timing Diagram, Internal Clock Divided By 1
RM0453 Advanced-control timer (TIM1) Figure 131. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 34 35 36 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31078V2 Figure 132. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT... -
Page 728: Figure 133. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timer (TIM1) RM0453 Figure 133. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31080V2 Figure 134. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register... -
Page 729: Figure 135. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded)
RM0453 Advanced-control timer (TIM1) Figure 135. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31082V3 Figure 136. - Page 730 Advanced-control timer (TIM1) RM0453 Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1.
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Page 731: Figure 137. Counter Timing Diagram, Internal Clock Divided By 1
RM0453 Advanced-control timer (TIM1) Figure 137. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT 03 02 01 00 34 33 32 Counter register Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) MS31184V1 Figure 138. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT... -
Page 732: Figure 139. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timer (TIM1) RM0453 Figure 139. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0001 0000 0000 0001 Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31186V1 Figure 140. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register... -
Page 733: Figure 141. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
RM0453 Advanced-control timer (TIM1) Figure 141. Counter timing diagram, update event when repetition counter is not used CK_PSC Timerclock = CK_CNT 30 2F Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31188V1 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the... -
Page 734: Figure 142. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
Advanced-control timer (TIM1) RM0453 DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •... -
Page 735: Figure 143. Counter Timing Diagram, Internal Clock Divided By 2
RM0453 Advanced-control timer (TIM1) Figure 143. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0003 0002 0001 0000 0001 0002 0003 Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31190V1 Figure 144. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timerclock = CK_CNT... -
Page 736: Figure 145. Counter Timing Diagram, Internal Clock Divided By N
Advanced-control timer (TIM1) RM0453 Figure 145. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31192V1 Figure 146. Counter timing diagram, update event with ARPE=1 (counter underflow) CK_PSC Timerclock = CK_CNT 05 04 03 02... -
Page 737: Figure 147. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow)
RM0453 Advanced-control timer (TIM1) Figure 147. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_PSC Timer clock = CK_CNT Counter register 31 30 2F F8 F9 FA FB FC Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active... -
Page 738: Figure 148. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
Advanced-control timer (TIM1) RM0453 In Center aligned mode, for odd values of RCR, the update event occurs either on the overflow or on the underflow depending on when the RCR register was written and when the counter was launched: if the RCR was written before launching the counter, the UEV occurs on the underflow. -
Page 739: Figure 149. External Trigger Input Block
RM0453 Advanced-control timer (TIM1) 25.3.4 External trigger input The timer features an external trigger input ETR. It can be used as: • external clock (external clock mode 2, see Section 25.3.5) • trigger for the slave mode (see Section 25.3.26) •... -
Page 740: Figure 151. Control Circuit In Normal Mode, Internal Clock Divided By 1
Advanced-control timer (TIM1) RM0453 25.3.5 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Encoder mode Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed... -
Page 741: Figure 152. Ti2 External Clock Connection Example
RM0453 Advanced-control timer (TIM1) Figure 152. TI2 external clock connection example TIMx_SMCR TS[4:0] TI2F TI1F Encoder mode ITRx 000xx TIMx_CH2 TI1_ED TRGI External clock 00100 mode 1 CK_PSC TI1FP1 TI2[0] 00101 TI2F_Rising External clock Edge TI2FP2 ETRF 00110 Filter TI2[1..15] detector mode 2 ETRF... -
Page 742: Figure 153. Control Circuit In External Clock Mode 1
Advanced-control timer (TIM1) RM0453 Figure 153. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 MS31087V2 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. -
Page 743: Figure 155. Control Circuit In External Clock Mode 2
RM0453 Advanced-control timer (TIM1) As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register. -
Page 744: Figure 156. Capture/Compare Channel (Example: Channel 1 Input Stage)
Advanced-control timer (TIM1) RM0453 25.3.6 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), an input stage for capture (with digital filter, multiplexing, and prescaler, except for channels 5 and 6) and an output stage (with comparator and output control). Figure 156 Figure 159 give an overview of one Capture/Compare channel. -
Page 745: Figure 158. Output Stage Of Capture/Compare Channel (Channel 1, Idem Ch. 2 And 3)
RM0453 Advanced-control timer (TIM1) Figure 158. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) TIMx_SMCR OCCS OCREF_CLR To the master mode controller ETRF Output enable ‘0’ circuit ocref_clr_int OC1REFC OC1REF OC1_DT CC1P CNT>CCR1 Output Output Dead-time TIM1_CCER mode CNT=CCR1... -
Page 746: Figure 160. Output Stage Of Capture/Compare Channel (Channel 5, Idem Ch. 6)
Advanced-control timer (TIM1) RM0453 Figure 160. Output stage of capture/compare channel (channel 5, idem ch. 6) TIMx_SMCR OCCS To the master OCREF_CLR mode controller ETRF ocref_clr_int ‘0’ Output CNT > CCR5 Output enable OC5REF mode circuit CNT = CCR5 controller CC5E CC5P CC5E TIM1_CCER... - Page 747 RM0453 Advanced-control timer (TIM1) detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP bits to 0 in the TIMx_CCER register (rising edge in this case). Program the input prescaler.
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Page 748: Figure 161. Pwm Input Mode Timing
Advanced-control timer (TIM1) RM0453 Select the proper TI1x source (internal or external) with the TI1SEL[3:0] bits in the TIMx_TISEL register. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P and CC1NP bits to ‘0’... - Page 749 RM0453 Advanced-control timer (TIM1) 25.3.10 Output compare mode This function is used to control an output waveform or indicate when a period of time has elapsed. Channels 1 to 4 can be output, while Channel 5 and 6 are only available inside the device (for instance, for compound waveform generation or for ADC triggering).
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Page 750: Figure 162. Output Compare Mode, Toggle On Oc1
Advanced-control timer (TIM1) RM0453 Figure 162. Output compare mode, toggle on OC1 Write B201h in the CC1R register 003B B200 B201 TIM1_CNT 0039 003A B201 003A TIM1_CCR1 OC1REF= OC1 Match detected on CCR1 Interrupt generated if enabled MS31092V1 25.3.11 PWM mode Pulse Width Modulation mode allows a signal to be generated with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. -
Page 751: Figure 163. Edge-Aligned Pwm Waveforms (Arr=8)
RM0453 Advanced-control timer (TIM1) PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 726. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <... -
Page 752: Figure 164. Center-Aligned Pwm Waveforms (Arr=8)
Advanced-control timer (TIM1) RM0453 TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting) on page 733. Figure 164 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, •... - Page 753 RM0453 Advanced-control timer (TIM1) in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
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Page 754: Figure 165. Generation Of 2 Phase-Shifted Pwm Signals With 50% Duty Cycle
Advanced-control timer (TIM1) RM0453 Figure 165. Generation of 2 phase-shifted PWM signals with 50% duty cycle Counter register OC1REFC CCR1=0 CCR2=8 OC3REFC CCR3=3 CCR4=5 MS33117V1 25.3.13 Combined PWM mode Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. -
Page 755: Figure 166. Combined Pwm Mode On Channel 1 And 3
RM0453 Advanced-control timer (TIM1) Figure 166. Combined PWM mode on channel 1 and 3 OC2’ OC1’ OC1REF OC2REF OC1REF’ OC2REF’ OC1REFC OC1REFC’ OC1REFC = OC1REF AND OC2REF OC1REFC’ = OC1REF’ OR OC2REF’ MS31094V1 25.3.14 Combined 3-phase PWM mode Combined 3-phase PWM mode allows one to three center-aligned PWM signals to be generated with a single programmable signal ANDed in the middle of the pulses. -
Page 756: Figure 167. 3-Phase Combined Pwm Signals With Multiple Trigger Pulses Per Period
Advanced-control timer (TIM1) RM0453 Figure 167. 3-phase combined PWM signals with multiple trigger pulses per period Counter OC5ref OC1refC OC2refC OC3refC Preload Active OC4ref OC6ref TRGO2 MS33102V1 The TRGO2 waveform shows how the ADC can be synchronized on given 3-phase PWM signals. -
Page 757: Figure 168. Complementary Output With Dead-Time Insertion
RM0453 Advanced-control timer (TIM1) Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: •... -
Page 758: Figure 170. Dead-Time Waveforms With Delay Greater Than The Positive Pulse
Advanced-control timer (TIM1) RM0453 Figure 170. Dead-time waveforms with delay greater than the positive pulse OCxREF OCxN delay MS31097V1 The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 25.4.20: TIM1 break and dead-time register (TIM1_BDTR) for delay calculation. - Page 759 RM0453 Advanced-control timer (TIM1) The output enable signal and output levels during break are depending on several control bits: – the MOE bit in TIMx_BDTR register allows the outputs to be enabled/disabled by software and is reset in case of break or break2 event. –...
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Page 760: Figure 171. Break And Break2 Circuitry Overview
Advanced-control timer (TIM1) RM0453 All sources are ORed before entering the timer BRK or BRK2 inputs, as per Figure 171 below. Figure 171. Break and Break2 circuitry overview Lockup LOCK Core Lockup PVD LOCK System break requests SBIF flag Parity LOCK RAM parity Error ECC LOCK Double ECC Error... - Page 761 RM0453 Advanced-control timer (TIM1) When one of the breaks occurs (selected level on one of the break inputs): • The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or even releasing the control to the GPIO controller (selected by the OSSI bit). This feature is enabled even if the MCU oscillator is off.
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Page 762: Figure 172. Various Output Behavior In Response To A Break Event On Brk (Ossi = 1)
Advanced-control timer (TIM1) RM0453 Figure 172. Various output behavior in response to a break event on BRK (OSSI = 1) BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay... -
Page 763: Table 176. Behavior Of Timer Outputs Versus Brk/Brk2 Inputs
RM0453 Advanced-control timer (TIM1) The two break inputs have different behaviors on timer outputs: – The BRK input can either disable (inactive state) or force the PWM outputs to a predefined safe state. – BRK2 can only disable (inactive state) the PWM outputs. The BRK has a higher priority than BRK2 input, as described in Table 176. -
Page 764: Figure 174. Pwm Output State Following Brk Assertion (Ossi=0)
Advanced-control timer (TIM1) RM0453 Figure 174. PWM output state following BRK assertion (OSSI=0) I/O state defined by the GPIO controller (HI-Z) Deadtime I/O state I/O state defined by the GPIO controller (HI-Z) Active Inactive Disabled MS34107V1 25.3.17 Bidirectional break inputs The TIM1 are featuring bidirectional break I/Os, as represented on Figure 175. -
Page 765: Table 177. Break Protection Disarming Conditions
RM0453 Advanced-control timer (TIM1) Table 177. Break protection disarming conditions BKDIR BKDSRM Break protection state (BK2DIR) (BK2DSRM) Armed Armed Disarmed Armed Arming and re-arming break circuitry The break circuitry (in input or bidirectional mode) is armed by default (peripheral reset configuration). -
Page 766: Figure 176. Clearing Timx Ocxref
Advanced-control timer (TIM1) RM0453 25.3.18 Clearing the OCxREF signal on an external event The OCxREF signal of a given channel can be cleared when a high level is applied on the ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1). OCxREF remains low until the next transition to the active state, on the following PWM cycle. -
Page 767: Figure 177. 6-Step Generation, Com Example (Ossr=1)
RM0453 Advanced-control timer (TIM1) 25.3.19 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus one can program in advance the configuration for the next step and change the configuration of all the channels at the same time. -
Page 768: Figure 178. Example Of One Pulse Mode
Advanced-control timer (TIM1) RM0453 25.3.20 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. - Page 769 RM0453 Advanced-control timer (TIM1) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
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Page 770: Figure 179. Retriggerable One Pulse Mode
Advanced-control timer (TIM1) RM0453 Figure 179. Retriggerable one pulse mode TRGI Counter Output MS33106V2 25.3.22 Encoder interface mode To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’... -
Page 771: Table 178. Counting Direction Versus Encoder Signals
RM0453 Advanced-control timer (TIM1) Table 178. Counting direction versus encoder signals Level on TI1FP1 signal TI2FP2 signal opposite signal (TI1FP1 Active edge for TI2, Rising Falling Rising Falling TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count... -
Page 772: Figure 181. Example Of Encoder Interface Mode With Ti1Fp1 Polarity Inverted
Advanced-control timer (TIM1) RM0453 Figure 181 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 181. Example of encoder interface mode with TI1FP1 polarity inverted. forward jitter backward jitter forward Counter down down MS33108V1... -
Page 773: Figure 182. Measuring Time Interval Between Edges On 3 Signals
RM0453 Advanced-control timer (TIM1) 25.3.24 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of an XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3. - Page 774 Advanced-control timer (TIM1) RM0453 Example: one wants to change the PWM configuration of the advanced-control timer TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers. • Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the TIMx_CR2 register to ‘1’, •...
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Page 775: Figure 183. Example Of Hall Sensor Interface
RM0453 Advanced-control timer (TIM1) Figure 183. Example of Hall sensor interface TIH1 TIH2 TIH3 Counter (CNT) (CCR2) CCR1 C7A3 C7A8 C794 C7A5 C7AB C796 TRGO=OC2REF OC1N OC2N OC3N Write CCxE, CCxNE and OCxM for next step MS32672V1 RM0453 Rev 5 775/1450... -
Page 776: Figure 184. Control Circuit In Reset Mode
Advanced-control timer (TIM1) RM0453 25.3.26 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. Refer to Section 26.3.19: Timer synchronization for details. They can be synchronized in several modes: Reset mode, Gated mode, and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. -
Page 777: Figure 185. Control Circuit In Gated Mode
RM0453 Advanced-control timer (TIM1) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000). -
Page 778: Figure 186. Control Circuit In Trigger Mode
Advanced-control timer (TIM1) RM0453 register. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). • Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=00110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. -
Page 779: Figure 187. Control Circuit In External Clock Mode 2 + Trigger Mode
RM0453 Advanced-control timer (TIM1) In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: –... - Page 780 Advanced-control timer (TIM1) RM0453 25.3.27 ADC synchronization The timer can generate an ADC triggering event with various internal signals, such as reset, enable or compare events. It is also possible to generate a pulse issued by internal edge detectors, such as: –...
- Page 781 RM0453 Advanced-control timer (TIM1) This is done in the following steps: Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers.
- Page 782 Advanced-control timer (TIM1) RM0453 25.4 TIM1 registers Refer to for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 25.4.1 TIM1 control register 1 (TIM1_CR1) Address offset: 0x00 Reset value: 0x0000 UIFRE Res.
- Page 783 RM0453 Advanced-control timer (TIM1) Bit 4 DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source...
- Page 784 Advanced-control timer (TIM1) RM0453 Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 MMS2[3:0]: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: 0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2).
- Page 785 RM0453 Advanced-control timer (TIM1) Bit 12 OIS3: Output Idle state 3 (OC3 output) Refer to OIS1 bit Bit 11 OIS2N: Output Idle state 2 (OC2N output) Refer to OIS1N bit Bit 10 OIS2: Output Idle state 2 (OC2 output) Refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0...
- Page 786 Advanced-control timer (TIM1) RM0453 Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note: This bit acts only on channels that have a complementary output.
- Page 787 RM0453 Advanced-control timer (TIM1) Bits 13:12 ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of f frequency. A CK_INT prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
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Page 788: Table 179. Tim1 Internal Trigger Connection
Advanced-control timer (TIM1) RM0453 Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. - Page 789 RM0453 Advanced-control timer (TIM1) Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bit 13 COMDE: COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled...
- Page 790 Advanced-control timer (TIM1) RM0453 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 25.4.5...
- Page 791 RM0453 Advanced-control timer (TIM1) Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bit 8 B2IF: Break 2 interrupt flag...
- Page 792 Advanced-control timer (TIM1) RM0453 Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
- Page 793 RM0453 Advanced-control timer (TIM1) Bit 2 CC2G: Capture/Compare 2 generation Refer to CC1G description Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
- Page 794 Advanced-control timer (TIM1) RM0453 Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC.
- Page 795 RM0453 Advanced-control timer (TIM1) corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Output compare mode: Res.
- Page 796 Advanced-control timer (TIM1) RM0453 Bits 16, 6:4 OC1M[3:0]: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
- Page 797 RM0453 Advanced-control timer (TIM1) Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
- Page 798 Advanced-control timer (TIM1) RM0453 Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 IC4F[3:0]: Input capture 4 filter Refer to IC1F[3:0] description. Bits 11:10 IC4PSC[1:0]: Input capture 4 prescaler Refer to IC1PSC[1:0] description. Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input.
- Page 799 RM0453 Advanced-control timer (TIM1) Bits 31:25 Reserved, must be kept at reset value. Bits 23:17 Reserved, must be kept at reset value. Bit 15 OC4CE: Output compare 4 clear enable Refer to OC1CE description. Bits 24, 14:12 OC4M[3:0]: Output compare 4 mode Refer to OC3M[3:0] description.
- Page 800 Advanced-control timer (TIM1) RM0453 25.4.11 TIM1 capture/compare enable register (TIM1_CCER) Address offset: 0x20 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC6P CC6E Res. Res. CC5P CC5E CC4NP Res. CC4P CC4E CC3NP CC3NE CC3P CC3E CC2NP CC2NE CC2P...
- Page 801 RM0453 Advanced-control timer (TIM1) Bit 5 CC2P: Capture/Compare 2 output polarity Refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable Refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high. 1: OC1N active low.
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Page 802: Table 180. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
Advanced-control timer (TIM1) RM0453 Bit 0 CC1E: Capture/Compare 1 output enable 0: Capture mode disabled / OC1 is not active (see below) 1: Capture mode enabled / OC1 signal is output on the corresponding output pin When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. - Page 803 RM0453 Advanced-control timer (TIM1) 25.4.12 TIM1 counter (TIM1_CNT) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNT[15:0] Bit 31 UIFCPY: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.
- Page 804 Advanced-control timer (TIM1) RM0453 25.4.15 TIM1 repetition counter register (TIM1_RCR) Address offset: 0x30 Reset value: 0x0000 REP[15:0] Bits 15:0 REP[15:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
- Page 805 RM0453 Advanced-control timer (TIM1) 25.4.17 TIM1 capture/compare register 2 (TIM1_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
- Page 806 Advanced-control timer (TIM1) RM0453 25.4.19 TIM1 capture/compare register 4 (TIM1_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE).
- Page 807 RM0453 Advanced-control timer (TIM1) Bit 28 BKBID: Break Bidirectional 0: Break input BRK in input mode 1: Break input BRK in bidirectional mode In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode.
- Page 808 Advanced-control timer (TIM1) RM0453 Bits 23:20 BK2F[3:0]: Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK2 acts asynchronously 0001: f...
- Page 809 RM0453 Advanced-control timer (TIM1) Bit 15 MOE: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.
- Page 810 Advanced-control timer (TIM1) RM0453 Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section 25.4.11: TIM1 capture/compare enable register (TIM1_CCER)).
- Page 811 RM0453 Advanced-control timer (TIM1) Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers.
- Page 812 Advanced-control timer (TIM1) RM0453 Bits 31:0 DMAB[31:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
- Page 813 RM0453 Advanced-control timer (TIM1) Res. Res. Res. Res. Res. Res. Res. OC6M[3] Res. Res. Res. Res. Res. Res. Res. OC5M[3] OC6M[2:0] OC6FE Res. Res. OC5M[2:0] OC5PE OC5FE Res. Res. Bits 31:25 Reserved, must be kept at reset value. Bits 23:17 Reserved, must be kept at reset value. Bit 15 OC6CE: Output compare 6 clear enable Refer to OC1CE description.
- Page 814 Advanced-control timer (TIM1) RM0453 Bit 31 GC5C3: Group Channel 5 and Channel 3 Distortion on Channel 3 output: 0: No effect of OC5REF on OC3REFC 1: OC3REFC is the logical AND of OC3REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2).
- Page 815 RM0453 Advanced-control timer (TIM1) 25.4.27 TIM1 alternate function option register 1 (TIM1_AF1) Address offset: 0x60 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[3:2] ETRSEL[1:0] Res. Res. BKINP Res. Res. Res.
- Page 816 Advanced-control timer (TIM1) RM0453 Bit 2 BKCMP2E: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is ‘ORed’ with the other BRK sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
- Page 817 RM0453 Advanced-control timer (TIM1) Bit 10 BK2CMP1P: BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P polarity bit. 0: COMP1 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1) 1: COMP1 input polarity is inverted (active high if BK2P=0, active low if BK2P=1) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
- Page 818 Advanced-control timer (TIM1) RM0453 25.4.29 TIM1 timer input selection register (TIM1_TISEL) Address offset: 0x68 Reset value: 0x0000 0000 Res. Res. Res. Res. TI4SEL[3:0] Res. Res. Res. Res. TI3SEL[3:0] Res. Res. Res. Res. TI2SEL[3:0] Res. Res. Res. Res. TI1SEL[3:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 TI4SEL[3:0]: selects TI4[0] to TI4[15] input 0000: TIM1_CH4 input Others: Reserved...
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Page 819: Table 181. Tim1 Register Map And Reset Values
RM0453 Advanced-control timer (TIM1) 25.4.30 TIM1 register map TIM1 registers are mapped as 16-bit addressable registers as described in the table below: Table 181. TIM1 register map and reset values Register Offset name TIM1_CR1 [1:0] [1:0] 0x00 Reset value TIM1_CR2 MMS2[3:0] [2:0] 0x04... - Page 820 Advanced-control timer (TIM1) RM0453 Table 181. TIM1 register map and reset values (continued) Register Offset name TIM1_CNT CNT[15:0] 0x24 Reset value TIM1_PSC PSC[15:0] 0x28 Reset value TIM1_ARR ARR[15:0] 0x2C Reset value TIM1_RCR REP[15:0] 0x30 Reset value TIM1_CCR1 CCR1[15:0] 0x34 Reset value TIM1_CCR2 CCR2[15:0] 0x38...
- Page 821 RM0453 Advanced-control timer (TIM1) Table 181. TIM1 register map and reset values (continued) Register Offset name TIM1_CCMR3 OC6M OC5M Output [2:0] [2:0] 0x54 Compare mode Reset value TIM1_CCR5 CCR5[15:0] 0x58 Reset value TIM1_CCR6 CCR6[15:0] 0x5C Reset value TIM1_AF1 ETRSEL 0x60 [3:0] Reset value TIM1_AF2...
- Page 822 General-purpose timer (TIM2) RM0453 General-purpose timer (TIM2) 26.1 TIM2 introduction The general-purpose timer TIM2 consists of a 32-bit auto-reload counter driven by a programmable prescaler. The timer may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
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Page 823: Figure 188. General-Purpose Timer Block Diagram
RM0453 General-purpose timer (TIM2) Figure 188. General-purpose timer block diagram Internal clock (CK_INT) From RCC Trigger ETRF controller TRGO Polarity selection & edge ETRP Input filter TIMx_ETR detector & prescaler to other timers to peripherals ITR[0..15] Slave TRGI Reset, enable, count controller mode TI1F_ED... - Page 824 General-purpose timer (TIM2) RM0453 26.3 TIM2 functional description 26.3.1 Time-base unit The main block of the programmable timer is a 32-bit counter with its related auto-reload register. The counter can count up, down or both up and down but also down or both up and down.
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Page 825: Figure 189. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0453 General-purpose timer (TIM2) Figure 189. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 190. -
Page 826: Figure 191. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timer (TIM2) RM0453 26.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller). -
Page 827: Figure 192. Counter Timing Diagram, Internal Clock Divided By 2
RM0453 General-purpose timer (TIM2) Figure 192. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0000 0002 0003 0034 0035 0036 0001 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V2 Figure 193. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT... -
Page 828: Figure 194. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timer (TIM2) RM0453 Figure 194. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31081V2 Figure 195. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT... -
Page 829: Figure 196. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
RM0453 General-purpose timer (TIM2) Figure 196. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timerclock = CK_CNT Counter register F1 F2 F3 F4 F5 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register... -
Page 830: Figure 197. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timer (TIM2) RM0453 The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 197. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 01 00 34 33 32 Counter underflow (cnt_udf) Update event (UEV) -
Page 831: Figure 199. Counter Timing Diagram, Internal Clock Divided By 4
RM0453 General-purpose timer (TIM2) Figure 199. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0001 0000 0000 0001 Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31186V1 Figure 200. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register... -
Page 832: Figure 201. Counter Timing Diagram, Update Event
General-purpose timer (TIM2) RM0453 Figure 201. Counter timing diagram, Update event CK_PSC Timerclock = CK_CNT 30 2F Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31188V1 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) –... -
Page 833: Figure 202. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
RM0453 General-purpose timer (TIM2) DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •... -
Page 834: Figure 203. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timer (TIM2) RM0453 Figure 203. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0000 0002 0003 0003 0002 0001 0001 Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31190V1 Figure 204. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timerclock = CK_CNT... -
Page 835: Figure 205. Counter Timing Diagram, Internal Clock Divided By N
RM0453 General-purpose timer (TIM2) Figure 205. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31192V1 Figure 206. Counter timing diagram, Update event with ARPE=1 (counter underflow) CK_PSC Timerclock = CK_CNT 05 04 03 02... -
Page 836: Figure 207. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow)
General-purpose timer (TIM2) RM0453 Figure 207. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_PSC Timer clock = CK_CNT Counter register F8 F9 FA FB FC 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active... -
Page 837: Figure 208. Control Circuit In Normal Mode, Internal Clock Divided By 1
RM0453 General-purpose timer (TIM2) Figure 208. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 33 34 35 36 03 04 05 MS31085V2 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. -
Page 838: Figure 210. Control Circuit In External Clock Mode 1
General-purpose timer (TIM2) RM0453 Note: The capture prescaler is not used for triggering, so it does not need to be configured. Select rising edge polarity by writing CC2P=0 and CC2NP=0 and CC2NP=0 in the TIMx_CCER register. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register. -
Page 839: Figure 211. External Trigger Input Block
RM0453 General-purpose timer (TIM2) Figure 211. External trigger input block TI2F TI1F Encoder ETR input or LSE mode TRGI External clock mode 1 CK_PSC ETRP Divider External clock ETRF ETR1..15 inputs from Filter /1, /2, /4, /8 mode 2 on-chip sources downcounter CK_INT Internal clock... -
Page 840: Figure 212. Control Circuit In External Clock Mode 2
General-purpose timer (TIM2) RM0453 Figure 212. Control circuit in external clock mode 2 f CK_INT CNT_EN ETRP ETRF Counter clock = CK_CNT =CK_PSC Counter register MSv33111V3 26.3.4 Capture/Compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). -
Page 841: Figure 214. Capture/Compare Channel 1 Main Circuit
RM0453 General-purpose timer (TIM2) Figure 214. Capture/Compare channel 1 main circuit APB Bus MCU-peripheral interface Input mode Output mode 16/32-bit CC1S[1] Capture/compare preload register CC1S[0] CC1S[1] CC1S[0] Compare IC1PS Capture transfer CC1E OC1PE OC1PE compare shadow register CC1G TIMx_CCMR1 (from time Comparator TIMx_EGR base unit) - Page 842 General-purpose timer (TIM2) RM0453 26.3.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
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Page 843: Figure 216. Pwm Input Mode Timing
RM0453 General-purpose timer (TIM2) 26.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •... - Page 844 General-purpose timer (TIM2) RM0453 26.3.7 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (ocxref/OCx) to its active level, one just needs to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register.
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Page 845: Figure 217. Output Compare Mode, Toggle On Oc1
RM0453 General-purpose timer (TIM2) The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 217. -
Page 846: Figure 218. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timer (TIM2) RM0453 cleared by an external event through the ETR signal until the next PWM period), the OCREF signal is asserted only: • When the result of the comparison or • When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from the “frozen”... - Page 847 RM0453 General-purpose timer (TIM2) Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Downcounting mode on page 829. In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then ocxref is held at 100%.
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Page 848: Figure 219. Center-Aligned Pwm Waveforms (Arr=8)
General-purpose timer (TIM2) RM0453 Figure 219. Center-aligned PWM waveforms (ARR=8) Counter register OCxREF CCRx = 4 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx=7 CMS=10 or 11 CCxIF ‘1’ OCxREF CCRx=8 CMS=01 CCxIF CMS=10 CMS=11 ‘1’ OCxREF CCRx>8 CMS=01 CCxIF CMS=10 CMS=11 ‘0’... -
Page 849: Figure 220. Generation Of 2 Phase-Shifted Pwm Signals With 50% Duty Cycle
RM0453 General-purpose timer (TIM2) 26.3.10 Asymmetric PWM mode Asymmetric mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of TIMx_CCRx registers. -
Page 850: Figure 221. Combined Pwm Mode On Channels 1 And 3
General-purpose timer (TIM2) RM0453 When a given channel is used as combined PWM channel, its secondary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2). Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones. -
Page 851: Figure 222. Clearing Timx Ocxref
RM0453 General-purpose timer (TIM2) The OCxREF signal for a given channel can be reset by applying a high level on the ETRF input (OCxCE enable bit set to 1 in the corresponding TIMx_CCMRx register). OCxREF remains low until the next transition to the active state, on the following PWM cycle. This function can be used only in the output compare and PWM modes. -
Page 852: Figure 223. Example Of One-Pulse Mode
General-purpose timer (TIM2) RM0453 26.3.13 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. - Page 853 RM0453 General-purpose timer (TIM2) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
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Page 854: Figure 224. Retriggerable One-Pulse Mode
General-purpose timer (TIM2) RM0453 Figure 224. Retriggerable one-pulse mode. TRGI Counter Output MS33106V2 26.3.15 Encoder interface mode To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges. -
Page 855: Table 182. Counting Direction Versus Encoder Signals
RM0453 General-purpose timer (TIM2) Table 182. Counting direction versus encoder signals Level on opposite TI1FP1 signal TI2FP2 signal Active edge signal (TI1FP1 for Rising Falling Rising Falling TI2, TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count... -
Page 856: Figure 226. Example Of Encoder Interface Mode With Ti1Fp1 Polarity Inverted
General-purpose timer (TIM2) RM0453 Figure 226. Example of encoder interface mode with TI1FP1 polarity inverted forward jitter backward jitter forward Counter down down MS33108V1 The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. Dynamic information can be obtained (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. -
Page 857: Figure 227. Control Circuit In Reset Mode
RM0453 General-purpose timer (TIM2) 26.3.18 Timers and external trigger synchronization The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. -
Page 858: Figure 228. Control Circuit In Gated Mode
General-purpose timer (TIM2) RM0453 Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so it does not need to be configured. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. -
Page 859: Figure 229. Control Circuit In Trigger Mode
RM0453 General-purpose timer (TIM2) CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=00110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. -
Page 860: Figure 230. Control Circuit In External Clock Mode 2 + Trigger Mode
General-purpose timer (TIM2) RM0453 A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input. -
Page 861: Figure 232. Master/Slave Connection Example With 1 Channel Only Timers
RM0453 General-purpose timer (TIM2) Figure 232. Master/slave connection example with 1 channel only timers TIM_mstr TIM_slv Clock Prescaler Counter Output Slave tim_oc1 tim_itr CK_PSC mode control control Compare 1 Prescaler Counter Input TIM_CH1 trigger selection MSv65225V1 Note: The timers with one channel only (see Figure 232) do not feature a master mode. -
Page 862: Figure 233. Gating Tim2 With Oc1Ref Of Tim1
General-purpose timer (TIM2) RM0453 Configure TIM1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register). Configure the TIM1 OC1REF waveform (TIM1_CCMR1 register). Configure TIM2 to get the input trigger from TIM1 (TS=00000 in the TIM2_SMCR register). -
Page 863: Figure 234. Gating Tim2 With Enable Of Tim1
RM0453 General-purpose timer (TIM2) Figure 234. Gating TIM2 with Enable of TIM1 CK_INT TIM1-CEN=CNT_EN TIM1-CNT_INIT TIM1-CNT TIM2-CNT TIM2-CNT_INIT TIM2-write CNT TIM2-TIF Write TIF = 0 MS32696V1 Using one timer to start another timer In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to Figure 231 for connections. -
Page 864: Figure 236. Triggering Tim2 With Enable Of Tim1
General-purpose timer (TIM2) RM0453 As in the previous example, both counters can be initialized before starting counting. Figure 236 shows the behavior with the same configuration as in Figure 235 but in trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register). Figure 236. - Page 865 RM0453 General-purpose timer (TIM2) As an example, the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) upon an update event, with the DMA transferring half words into the CCRx registers. This is done in the following steps: Configure the corresponding DMA channel as follows: –...
- Page 866 General-purpose timer (TIM2) RM0453 26.4 TIM2 registers In this section, “TIMx” should be understood as “TIM2” since there is only one instance of this type of timer for the products to which this reference manual applies. Refer to Section 1.2 for a list of abbreviations used in register descriptions.
- Page 867 RM0453 General-purpose timer (TIM2) Bit 4 DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source...
- Page 868 General-purpose timer (TIM2) RM0453 Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) Section 25.3.25: Interfacing with Hall sensors on page 773 See also Bits 6:4 MMS[2:0]: Master mode selection...
- Page 869 RM0453 General-purpose timer (TIM2) 26.4.3 TIM2 slave mode control register (TIM2_SMCR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TS[4:3] Res. Res. Res. SMS[3] ETPS[1:0] ETF[3:0] TS[2:0] OCCS SMS[2:0] Bits 31:22 Reserved, must be kept at reset value. Bits 19:17 Reserved, must be kept at reset value.
- Page 870 General-purpose timer (TIM2) RM0453 Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
- Page 871 RM0453 General-purpose timer (TIM2) Bits 21, 20, 6, 5, 4 TS[4:0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00000: Internal Trigger 0 (ITR0) 00001: Internal Trigger 1 (ITR1) 00010: Internal Trigger 2 (ITR2) 00011: Internal Trigger 3 (ITR3) 00100: TI1 Edge Detector (TI1F_ED) 00101: Filtered Timer Input 1 (TI1FP1)
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Page 872: Table 183. Tim2 Internal Trigger Connection
General-purpose timer (TIM2) RM0453 Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. - Page 873 RM0453 General-purpose timer (TIM2) Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled. Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled. 1: CC2 DMA request enabled. Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled.
- Page 874 General-purpose timer (TIM2) RM0453 Bits 15:13 Reserved, must be kept at reset value. Bit 12 CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag refer to CC1OF description Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input...
- Page 875 RM0453 General-purpose timer (TIM2) Bit 2 CC2IF: Capture/Compare 2 interrupt flag Refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). 0: No compare match / No input capture occurred 1: A compare match or an input capture occurred If channel CC1 is configured as output: this flag is set when the content of the counter...
- Page 876 General-purpose timer (TIM2) RM0453 Bit 2 CC2G: Capture/compare 2 generation Refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
- Page 877 RM0453 General-purpose timer (TIM2) Bits 9:8 CC2S[1:0]: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1.
- Page 878 General-purpose timer (TIM2) RM0453 26.4.8 TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) Address offset: 0x18 Reset value: 0x0000 0000 The same register can be used for output compare mode (this section) or for input capture mode (previous section). The direction of a channel is defined by configuring the corresponding CCxS bits.
- Page 879 RM0453 General-purpose timer (TIM2) Bits 16, 6:4 OC1M[3:0]: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
- Page 880 General-purpose timer (TIM2) RM0453 Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
- Page 881 RM0453 General-purpose timer (TIM2) Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC.
- Page 882 General-purpose timer (TIM2) RM0453 Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC.
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Page 883: Table 184. Output Control Bit For Standard Ocx Channels
RM0453 General-purpose timer (TIM2) Bit 7 CC2NP: Capture/Compare 2 output Polarity. Refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable. Refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 output Polarity. - Page 884 General-purpose timer (TIM2) RM0453 Address offset: 0x24 Reset value: 0x0000 0000 CNT[31:16] CNT[15:0] Bits 31:0 CNT[31:0]: counter value 26.4.13 TIM2 counter [alternate] (TIM2_CNT) Bit 31 of this register has two possible definitions depending on the value of UIFREMAP in TIMx_CR1 register: •...
- Page 885 RM0453 General-purpose timer (TIM2) 26.4.15 TIM2 auto-reload register (TIM2_ARR) Address offset: 0x2C Reset value: 0xFFFF FFFF ARR[31:16] ARR[15:0] Bits 31:0 ARR[31:0]: Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 26.3.1: Time-base unit on page 824 for more details about ARR update and behavior.
- Page 886 General-purpose timer (TIM2) RM0453 CCR2[31:16] CCR2[15:0] Bits 31:0 CCR2[31:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE).
- Page 887 RM0453 General-purpose timer (TIM2) CCR4[31:16] CCR4[15:0] Bits 31:0 CCR4[31:0]: Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE).
- Page 888 General-purpose timer (TIM2) RM0453 26.4.21 TIM2 DMA address for full transfer (TIM2_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the...
- Page 889 RM0453 General-purpose timer (TIM2) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[3:2] ETRSEL[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:18 Reserved, must be kept at reset value. Bits 17:14 ETRSEL[3:0]: ETR source selection These bits select the ETR input source.
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Page 890: Table 185. Tim2 Register Map And Reset Values
General-purpose timer (TIM2) RM0453 26.4.25 TIMx register map TIMx registers are mapped as described in the table below: Table 185. TIM2 register map and reset values Register Offset name TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS TIMx_SMCR ETF[3:0]... - Page 891 RM0453 General-purpose timer (TIM2) Table 185. TIM2 register map and reset values (continued) Register Offset name TIMx_CNT CNT[30:0] 0x24 Reset value TIMx_PSC PSC[15:0] 0x28 Reset value TIMx_ARR ARR[31:0] 0x2C Reset value 0x30 Reserved TIMx_CCR1 CCR1[31:0] 0x34 Reset value TIMx_CCR2 CCR2[31:0] 0x38 Reset value TIMx_CCR3...
- Page 892 General-purpose timer (TIM2) RM0453 Table 185. TIM2 register map and reset values (continued) Register Offset name TIM2_TISEL TI2SEL[3:0] TI1SEL[3:0] 0x68 Reset value Refer to Section 2.6 on page 71 for the register boundary addresses. 892/1450 RM0453 Rev 5...
- Page 893 RM0453 General-purpose timers (TIM16/TIM17) General-purpose timers (TIM16/TIM17) 27.1 TIM16/TIM17 introduction The TIM16/TIM17 timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
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Page 894: Figure 237. Tim16/Tim17 Block Diagram
General-purpose timers (TIM16/TIM17) RM0453 Figure 237. TIM16/TIM17 block diagram Internal clock (CK_INT) Counter Enable (CEN) REP register To other timers for Auto-reload register cross- Repetition trigerring Stop, clear or up/down counter CK_PSC CK_CNT CNT counter prescaler DTG registers CC1I TI1[0] TIMx_CH1 Input TIMx_CH1... - Page 895 RM0453 General-purpose timers (TIM16/TIM17) 27.3 TIM16/TIM17 functional description 27.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
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Page 896: Figure 238. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM16/TIM17) RM0453 Figure 238. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 239. - Page 897 RM0453 General-purpose timers (TIM16/TIM17) 27.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR).
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Page 898: Figure 240. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM16/TIM17) RM0453 Figure 240. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT 34 35 36 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31078V2 Figure 241. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT... -
Page 899: Figure 242. Counter Timing Diagram, Internal Clock Divided By 4
RM0453 General-purpose timers (TIM16/TIM17) Figure 242. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31080V2 Figure 243. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register... -
Page 900: Preloaded)
General-purpose timers (TIM16/TIM17) RM0453 Figure 244. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT 05 06 07 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31082V2 Figure 245. - Page 901 RM0453 General-purpose timers (TIM16/TIM17) 27.3.3 Repetition counter Section 27.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals. This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N counter overflows, where N is the...
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Page 902: Figure 246. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
General-purpose timers (TIM16/TIM17) RM0453 Figure 246. Update rate examples depending on mode and TIMx_RCR register settings Edge-aligned mode Upcounting Counter TIMx_CNT TIMx_RCR = 0 TIMx_RCR = 1 TIMx_RCR = 2 TIMx_RCR = 3 TIMx_RCR = 3 re-synchronization UEV (by SW) Update Event: preload registers transferred to active registers and update interrupt generated. -
Page 903: Figure 247. Control Circuit In Normal Mode, Internal Clock Divided By 1
RM0453 General-purpose timers (TIM16/TIM17) Figure 247 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. Figure 247. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN Counter initialization (internal) Counter clock = CK_CNT = CK_PSC Counter register 35 36 03 04 05... -
Page 904: Figure 249. Control Circuit In External Clock Mode 1
General-purpose timers (TIM16/TIM17) RM0453 Select the proper TI2[x] source (internal or external) with the TI2SEL[3:0] bits in the TIMx_TISEL register. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). -
Page 905: Figure 250. Capture/Compare Channel (Example: Channel 1 Input Stage)
RM0453 General-purpose timers (TIM16/TIM17) Figure 250. Capture/compare channel (example: channel 1 input stage) TI1F_ED To the slave mode controller TI1[0] TI1F_Rising TI1FP1 Filter Edge TI1[1..15] TI1F_Falling downcounter detector IC1PS Divider TI2FP1 /1, /2, /4, /8 ICF[3:0] CC1P TIMx_CCER TIMx_CCMR1 (from slave mode controller) TI2F_Rising (from channel 2) -
Page 906: Figure 252. Output Stage Of Capture/Compare Channel (Channel 1)
General-purpose timers (TIM16/TIM17) RM0453 Figure 252. Output stage of capture/compare channel (channel 1) To the master mode controller Output enable ‘0’ circuit OC1REFC OC1REF OC1_DT CC1P CNT>CCR1 Output Output Dead-time TIM1_CCER mode CNT=CCR1 selector generator controller OC1N_DT Output OC1N ‘0’ OC2REF enable circuit... - Page 907 RM0453 General-purpose timers (TIM16/TIM17) detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in the TIMx_CCER register (rising edge in this case). Program the input prescaler.
- Page 908 General-purpose timers (TIM16/TIM17) RM0453 When a match is found between the capture/compare register and the counter, the output compare function: • Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register).
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Page 909: Figure 253. Output Compare Mode, Toggle On Oc1
RM0453 General-purpose timers (TIM16/TIM17) Figure 253. Output compare mode, toggle on OC1 Write B201h in the CC1R register TIM1_CNT 0039 003A 003B B200 B201 B201 003A TIM1_CCR1 OC1REF= OC1 Match detected on CCR1 Interrupt generated if enabled MS31092V1 27.3.9 PWM mode Pulse Width Modulation mode allows a signal to be generated with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. -
Page 910: Figure 254. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM16/TIM17) RM0453 Figure 254. Edge-aligned PWM waveforms (ARR=8) Counter register OCXREF CCRx=4 CCxIF OCXREF CCRx=8 CCxIF ‘1’ OCXREF CCRx>8 CCxIF ‘0’ OCXREF CCRx=0 CCxIF MS31093V1 27.3.10 Complementary outputs and dead-time insertion The TIM16/TIM17 general-purpose timers can output one complementary signal and manage the switching-off and switching-on of the outputs. -
Page 911: Figure 255. Complementary Output With Dead-Time Insertion
RM0453 General-purpose timers (TIM16/TIM17) If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated. The following figures show the relationships between the output signals of the dead-time generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1, CCxE=1 and CCxNE=1 in these examples) Figure 255. -
Page 912: Figure 257. Dead-Time Waveforms With Delay Greater Than The Positive Pulse
General-purpose timers (TIM16/TIM17) RM0453 Figure 257. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay MS31097V1 The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 27.4.14: TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) on page 935 for delay calculation. - Page 913 RM0453 General-purpose timers (TIM16/TIM17) must be inserted (dummy instruction) before reading it correctly. This is because the write acts on the asynchronous signal whereas the read reflects the synchronous signal. When a break occurs (selected level on the break input): •...
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Page 914: Figure 258. Output Behavior In Response To A Break
General-purpose timers (TIM16/TIM17) RM0453 Figure 258. Output behavior in response to a break BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay OCxN (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay delay... -
Page 915: Table 186. Break Protection Disarming Conditions
RM0453 General-purpose timers (TIM16/TIM17) 27.3.12 Bidirectional break inputs The TIM16/TIM17 are featuring bidirectional break I/Os, as represented on Figure 259. They allow the following: • A board-level global break signal available for signaling faults to external MCUs or gate drivers, with a unique pin being both an input and an output status pin •... -
Page 916: Figure 259. Output Redirection
General-purpose timers (TIM16/TIM17) RM0453 The following procedure must be followed to re-arm the protection after a break event: • The BKDSRM bit must be set to release the output control • The software must wait until the system break condition disappears (if any) and clear the SBIF status flag (or clear it systematically before re-arming) •... -
Page 917: Figure 260. 6-Step Generation, Com Example (Ossr=1)
RM0453 General-purpose timers (TIM16/TIM17) Figure 260. 6-step generation, COM example (OSSR=1) Counter (CNT) tim_ocxref Write COM to 1 COM event CCxE = 1 CCxE = 1 Write OCxM to 0100 CCxNE = 0 CCxNE = 0 OCxM = 0010 (forced inactive) OCxM = 0100 tim_ocx Example 1... -
Page 918: Figure 261. Example Of One Pulse Mode
General-purpose timers (TIM16/TIM17) RM0453 27.3.14 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. - Page 919 RM0453 General-purpose timers (TIM16/TIM17) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
- Page 920 General-purpose timers (TIM16/TIM17) RM0453 The DMA controller destination is unique and must point to the virtual register TIMx_DMAR. On a given timer event, the timer launches a sequence of DMA requests (burst). Each write into the TIMx_DMAR register is actually redirected to one of the timer registers. The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length.
- Page 921 RM0453 General-purpose timers (TIM16/TIM17) For instance, if the destination's timer CK_INT clock is 4 times slower than the source timer, the OC1 pulse width must be 8 clock cycles. 27.3.19 Debug mode ® When the microcontroller enters debug mode (Cortex -M4 core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module.
- Page 922 General-purpose timers (TIM16/TIM17) RM0453 27.4 TIM16/TIM17 registers Refer to Section 1.2 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 27.4.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17) Address offset: 0x00 Reset value: 0x0000 UIFRE...
- Page 923 RM0453 General-purpose timers (TIM16/TIM17) Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow –...
- Page 924 General-purpose timers (TIM16/TIM17) RM0453 Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output.
- Page 925 RM0453 General-purpose timers (TIM16/TIM17) 27.4.4 TIMx status register (TIMx_SR)(x = 16 to 17) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. CC1OF Res. Res. COMIF Res. Res. Res. CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:10 Reserved, must be kept at reset value. Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode.
- Page 926 General-purpose timers (TIM16/TIM17) RM0453 Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
- Page 927 RM0453 General-purpose timers (TIM16/TIM17) 27.4.6 TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 16 to 17) Address offset: 0x18 Reset value: 0x0000 0000 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits.
- Page 928 General-purpose timers (TIM16/TIM17) RM0453 Bits 1:0 CC1S[1:0]: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’...
- Page 929 RM0453 General-purpose timers (TIM16/TIM17) Bits 16, 6:4 OC1M[3:0]: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
- Page 930 General-purpose timers (TIM16/TIM17) RM0453 27.4.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1NP CC1NE CC1P CC1E Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high...
- Page 931 RM0453 General-purpose timers (TIM16/TIM17) Bit 2 CC1NE: Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
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Page 932: Table 187. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
General-purpose timers (TIM16/TIM17) RM0453 Table 187. Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) Control bits Output states MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state Output Disabled (not driven by the timer: Hi-Z) OCx=0 OCxN=0, OCxN_EN=0 Output Disabled (not driven... - Page 933 RM0453 General-purpose timers (TIM16/TIM17) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNT[15:0] Bit 31 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0.
- Page 934 General-purpose timers (TIM16/TIM17) RM0453 27.4.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) Address offset: 0x30 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e.
- Page 935 RM0453 General-purpose timers (TIM16/TIM17) 27.4.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) Address offset: 0x44 Reset value: 0x0000 0000 Res. Res. Res. BKBID Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DSRM OSSR OSSI LOCK[1:0] DTG[7:0] Note:...
- Page 936 General-purpose timers (TIM16/TIM17) RM0453 Bit 14 AOE: Automatic output enable 0: MOE can be set only by software 1: MOE can be set by software or automatically at the next update event (if the break input is not be active) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
- Page 937 RM0453 General-purpose timers (TIM16/TIM17) Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 27.4.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) on page 930).
- Page 938 General-purpose timers (TIM16/TIM17) RM0453 Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers.
- Page 939 RM0453 General-purpose timers (TIM16/TIM17) 27.4.17 TIM16 option register 1 (TIM16_OR1) Address offset: 0x50 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 940 General-purpose timers (TIM16/TIM17) RM0453 Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low 1: BKIN input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
- Page 941 RM0453 General-purpose timers (TIM16/TIM17) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1_RMP[1:0] Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 TI1_RMP[1:0]: Timer 17 input 1 connection This bit is set and cleared by software.
- Page 942 General-purpose timers (TIM16/TIM17) RM0453 Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low 1: BKIN input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
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Page 943: Table 188. Tim16/Tim17 Register Map And Reset Values
RM0453 General-purpose timers (TIM16/TIM17) 27.4.23 TIM16/TIM17 register map TIM16/TIM17 registers are mapped as 16-bit addressable registers as described in the table below: Table 188. TIM16/TIM17 register map and reset values Register Offset name TIMx_CR1 [1:0] 0x00 Reset value TIMx_CR2 0x04 Reset value TIMx_DIER 0x0C... - Page 944 General-purpose timers (TIM16/TIM17) RM0453 Table 188. TIM16/TIM17 register map and reset values (continued) Register Offset name TIMx_RCR REP[7:0] 0x30 Reset value TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_BDTR DTG[7:0] 0x44 [1:0] Reset value TIMx_DCR DBL[4:0] DBA[4:0] 0x48 Reset value TIMx_DMAR DMAB[15:0] 0x4C Reset value TI1_...
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Page 945: Table 189. Stm32Wl5X Lptim Features
RM0453 Low-power timer (LPTIM) Low-power timer (LPTIM) 28.1 Introduction The LPTIM is a 16-bit timer that benefits from the ultimate developments in power consumption reduction. Thanks to its diversity of clock sources, the LPTIM is able to keep running in all power modes except for Standby mode. Given its capability to run even with no internal clock source, the LPTIM can be used as a “Pulse Counter”... -
Page 946: Table 190. Lptim Input/Output Pins
Low-power timer (LPTIM) RM0453 1. X = supported. 2. Wake-up supported from Stop 0, Stop 1 and Stop 2 modes. 3. Wake-up supported from Stop 0 and Stop 1 modes. 28.4 LPTIM functional description 28.4.1 LPTIM block diagram Figure 262. Low-power timer block diagram LPTIM Kernel clock domain Up/down... -
Page 947: Table 191. Lptim Internal Signals
RM0453 Low-power timer (LPTIM) Table 191. LPTIM internal signals Names Signal type Description lptim_pclk Digital input LPTIM APB clock domain lptim_ker_ck Digital input LPTIM kernel clock lptim_in1 Digital input Internal LPTIM input 1 lptim_in2 Digital input Internal LPTIM input 2 lptim_ext_trigx Digital input LPTIM external trigger input x... -
Page 948: Table 194. Lptim3 External Trigger Connection
Low-power timer (LPTIM) RM0453 Table 194. LPTIM3 external trigger connection TRIGSEL External trigger lptim_ext_trig0 GPIO pin as LPTIM3_ETR alternate function lptim_ext_trig1 lptim1_out lptim_ext_trig2 lptim2_out lptim_ext_trig3 lptim_ext_trig4 lptim_ext_trig5 lptim_ext_trig6 lptim_ext_trig7 Table 195. LPTIM1 input 1 connection lptim_in1 LPTIM1 input 1 connected to lptim_in1 GPIO pin as LPTIM1_IN1 alternate function lptim_in1... - Page 949 RM0453 Low-power timer (LPTIM) 28.4.4 LPTIM reset and clocks The LPTIM can be clocked using several clock sources. It can be clocked using an internal clock signal which can be any configurable internal clock source selectable through the RCC (see RCC section for more details). Also, the LPTIM can be clocked using an external clock signal injected on its external Input1.
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Page 950: Table 199. Prescaler Division Ratios
Low-power timer (LPTIM) RM0453 Figure 263. Glitch filter timing diagram CLKMUX Input Filter out 2 consecutive samples 2 consecutive samples Filtered MS32490V1 Note: In case no internal clock signal is provided, the digital filter must be deactivated by setting the CKFLT and TRGFLT bits to ‘0’. In that case, an external analog filter may be used to protect the LPTIM external inputs against glitches. -
Page 951: Figure 264. Lptim Output Waveform, Single Counting Mode Configuration When Repetition Register Content Is Different Than Zero (With Preload = 1)
RM0453 Low-power timer (LPTIM) The external triggers are considered asynchronous signals for the LPTIM. So after a trigger detection, a two-counter-clock period latency is needed before the timer starts running due to the synchronization. If a new trigger event occurs when the timer is already started it is ignored (unless timeout function is enabled). -
Page 952: And Set-Once Mode Activated (Wave Bit Is Set)
Low-power timer (LPTIM) RM0453 - Set-once mode activated: Note that when the WAVE bitfield in the LPTIM_CFGR register is set, the Set-once mode is activated. In this case, the counter is only started once following the first trigger, and any subsequent trigger event is discarded as shown in Figure 265. - Page 953 RM0453 Low-power timer (LPTIM) If the Continuous mode was previously selected, setting SNGSTRT switches the LPTIM to the One-shot mode. The counter (if active) stops as soon as an LPTIM update event is generated. If the One-shot mode was previously selected, setting CNTSTRT switches the LPTIM to the Continuous mode.
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Page 954: Figure 267. Waveform Generation
Low-power timer (LPTIM) RM0453 Figure 267. Waveform generation LPTIM_ARR Compare One shot Pol = 0 Set once One shot Pol = 1 Set once MS32467V2 28.4.11 Register update The LPTIM_ARR register and LPTIM_CMP register are updated immediately after the APB bus write operation or in synchronization with the next LPTIM update event if the timer is already started. - Page 955 RM0453 Low-power timer (LPTIM) 28.4.12 Counter mode The LPTIM counter can be used to count external events on the LPTIM Input1 or it can be used to count internal clock cycles. The CKSEL and COUNTMODE bits control which source is used for updating the counter. In case the LPTIM is configured to count external events on Input1, the counter can be updated following a rising edge, falling edge or both edges depending on the value written to the CKPOL[1:0] bits.
- Page 956 Low-power timer (LPTIM) RM0453 28.4.14 Timer counter reset In order to reset the content of LPTIM_CNT register to zero, two reset mechanisms are implemented: • The synchronous reset mechanism: the synchronous reset is controlled by the COUNTRST bit in the LPTIM_CR register. After setting the COUNTRST bitfield to '1', the reset signal is propagated in the LPTIM kernel clock domain.
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Page 957: Table 200. Encoder Counting Scenarios
RM0453 Low-power timer (LPTIM) To activate the Encoder mode the ENC bit has to be set to ‘1’. The LPTIM must first be configured in Continuous mode. When Encoder mode is active, the LPTIM counter is modified automatically following the speed and the direction of the incremental encoder. -
Page 958: Figure 268. Encoder Mode Counting Sequence
Low-power timer (LPTIM) RM0453 Figure 268. Encoder mode counting sequence Counter down MS32491V1 28.4.16 Repetition Counter The LPTIM features a repetition counter that decrements by 1 each time an LPTIM counter overflow event occurs. A repetition counter underflow event is generated when the repetition counter contains zero and the LPTIM counter overflows. -
Page 959: Different From Zero (With Preload = 1)
RM0453 Low-power timer (LPTIM) Figure 269. Continuous counting mode when repetition register LPTIM_RCR different from zero (with PRELOAD = 1) Repetition counter underflow event LPTIM_RCR Repetition counter LPTIM_ARR Preloaded registers updated Compare MSv47415V1 A repetition counter underflow event is systematically associated with LPTIM preloaded registers update (refer to section "Register update"... -
Page 960: Table 201. Effect Of Low-Power Modes On The Lptim
Low-power timer (LPTIM) RM0453 28.5 LPTIM low-power modes Table 201. Effect of low-power modes on the LPTIM Mode Description Sleep No effect. LPTIM interrupts cause the device to exit Sleep mode. If the LPTIM is clocked by an oscillator available in Stop mode, LPTIM is functional Stop and the interrupts cause the device to exit the Stop mode (refer to Section 28.3: LPTIM... - Page 961 RM0453 Low-power timer (LPTIM) Table 202. Interrupt events (continued) Interrupt event Description Interrupt flag is raised when the repetition counter underflows (or contains Update Event zero) and the LPTIM counter overflows. Repetition register REPOK is set by hardware to inform application that the APB bus write update Ok operation to the LPTIM_RCR register has been successfully completed.
- Page 962 Low-power timer (LPTIM) RM0453 Bit 4 ARROK: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.
- Page 963 RM0453 Low-power timer (LPTIM) Bit 3 CMPOKCF: Compare register update OK clear flag Writing 1 to this bit clears the CMPOK flag in the LPTIM_ISR register Bit 2 EXTTRIGCF: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register Bit 1 ARRMCF: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register Bit 0 CMPMCF: Compare match clear flag...
- Page 964 Low-power timer (LPTIM) RM0453 Bit 2 EXTTRIGIE: External trigger valid edge Interrupt Enable EXTTRIG interrupt disabled EXTTRIG interrupt enabled Bit 1 ARRMIE: Autoreload match Interrupt Enable ARRM interrupt disabled ARRM interrupt enabled Bit 0 CMPMIE: Compare match Interrupt Enable CMPM interrupt disabled CMPM interrupt enabled Caution: The LPTIM_IER register must only be modified when the LPTIM is disabled (ENABLE bit reset to ‘0’) 28.7.4...
- Page 965 RM0453 Low-power timer (LPTIM) Bit 21 WAVPOL: Waveform shape polarity The WAVPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers Bit 20 WAVE: Waveform shape The WAVE bit controls the output shape...
- Page 966 Low-power timer (LPTIM) RM0453 Bits 7:6 TRGFLT[1:0]: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as...
- Page 967 RM0453 Low-power timer (LPTIM) 28.7.5 LPTIM control register (LPTIM_CR) Address offset: 0x010 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. COUN Res. Res. Res. Res. Res. Res. Res. Res.
- Page 968 Low-power timer (LPTIM) RM0453 28.7.6 LPTIM compare register (LPTIM_CMP) Address offset: 0x014 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CMP[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CMP[15:0]: Compare value CMP is the compare value used by the LPTIM.
- Page 969 RM0453 Low-power timer (LPTIM) 28.7.8 LPTIM counter register (LPTIM_CNT) Address offset: 0x01C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNT[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CNT[15:0]: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values.
- Page 970 Low-power timer (LPTIM) RM0453 28.7.10 LPTIM2 option register (LPTIM2_OR) Address offset: 0x020 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
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Page 971: Table 203. Lptim Register Map And Reset Values
RM0453 Low-power timer (LPTIM) 28.7.12 LPTIM repetition register (LPTIM_RCR) Address offset: 0x028 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 31:8 Reserved, must be kept at reset value. - Page 972 Low-power timer (LPTIM) RM0453 Table 203. LPTIM register map and reset values (continued) Offset Register name LPTIM_CR 0x010 0 0 0 0 0 Reset value LPTIM_CMP [15:0] 0x014 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value ARR[15:0] LPTIM_ARR...
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Page 973: Figure 270. Irtim Internal Hardware Connections With Tim16 And Tim17
RM0453 Infrared interface (IRTIM) Infrared interface (IRTIM) An infrared interface (IRTIM) for remote control is available on the device. It can be used with an infrared LED to perform remote control functions. It uses internal connections withTIM16 and TIM17 as shown in Figure 270. -
Page 974: Figure 271. Independent Watchdog Block Diagram
Independent watchdog (IWDG) RM0453 Independent watchdog (IWDG) 30.1 Introduction The devices feature an embedded watchdog peripheral that offers a combination of high safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral detects and solves malfunctions due to software failure, and triggers system reset when the counter reaches a given timeout value. - Page 975 RM0453 Independent watchdog (IWDG) When the independent watchdog is started by writing the value 0x0000 CCCC in the IWDG key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). Whenever the key value 0x0000 AAAA is written in the IWDG key register (IWDG_KR), the...
- Page 976 Independent watchdog (IWDG) RM0453 30.3.3 Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the IWDG key register (IWDG_KR) is written by the software before the counter reaches end of count or if the downcounter is reloaded inside the window.
- Page 977 RM0453 Independent watchdog (IWDG) 30.4 IWDG registers Refer to Section 1.2 on page 59 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 30.4.1 IWDG key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) Res.
- Page 978 Independent watchdog (IWDG) RM0453 30.4.2 IWDG prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 979 RM0453 Independent watchdog (IWDG) 30.4.3 IWDG reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RL[11:0] Bits 31:12 Reserved, must be kept at reset value.
- Page 980 Independent watchdog (IWDG) RM0453 30.4.4 IWDG status register (IWDG_SR) Address offset: 0x0C Reset value: 0x0000 0000 (not reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
- Page 981 RM0453 Independent watchdog (IWDG) 30.4.5 IWDG window register (IWDG_WINR) Address offset: 0x10 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WIN[11:0] Bits 31:12 Reserved, must be kept at reset value.
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Page 982: Table 204. Iwdg Register Map And Reset Values
Independent watchdog (IWDG) RM0453 30.4.6 IWDG register map The following table gives the IWDG register map and reset values. Table 204. IWDG register map and reset values Register Offset name IWDG_KR KEY[15:0] 0x00 Reset value IWDG_PR PR[2:0] 0x04 Reset value IWDG_RLR RL[11:0] 0x08... - Page 983 RM0453 System window watchdog (WWDG) System window watchdog (WWDG) 31.1 Introduction The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the down-counter before the T6 bit is cleared.
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Page 984: Table 205. Wwdg Internal Input/Output Signals
System window watchdog (WWDG) RM0453 31.3.1 WWDG block diagram Figure 272. Watchdog block diagram WWDG CMP = 1 when Register interface T[6:0] > W[6:0] W[6:0] WWDG_CFR wwdg_out_rst WWDG_SR Write to WDGA WWDG_CR readback = 0x40 ? WWDG_CR wwdg_it preload EWIF cnt_out 7-bit downcounter (CNT) WDGTB... -
Page 985: Figure 273. Window Watchdog Timing Diagram
RM0453 System window watchdog (WWDG) 31.3.5 How to program the watchdog timeout Use the formula in Figure 273 to calculate the WWDG timeout. Warning: When writing to the WWDG_CR register, always write 1 in the T6 bit to avoid generating an immediate reset. Figure 273. - Page 986 System window watchdog (WWDG) RM0453 As an example, if APB frequency is 48 MHz, WDGTB[2:0] is set to 3 and T[5:0] is set to 63: ⁄ × × × t WWDG 48000 4096 43.69ms Refer to the datasheet for the minimum and maximum values of t WWDG 31.3.6 Debug mode...
- Page 987 RM0453 System window watchdog (WWDG) 31.5.1 WWDG control register (WWDG_CR) Address offset: 0x000 Reset value: 0x0000 007F Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
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Page 988: Table 206. Wwdg Register Map And Reset Values
System window watchdog (WWDG) RM0453 Bit 9 EWI: Early wake-up interrupt enable Set by software and cleared by hardware after a reset. When set, an interrupt occurs whenever the counter reaches the value 0x40. Bits 8:7 Reserved, must be kept at reset value. Bits 6:0 W[6:0]: 7-bit window value These bits contain the window value to be compared with the down-counter. - Page 989 RM0453 Real-time clock (RTC) Real-time clock (RTC) 32.1 Introduction The RTC provides an automatic wake-up to manage all low-power modes. The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time- of-day clock/calendar with programmable alarm interrupts. As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low-power mode or under reset).
- Page 990 Real-time clock (RTC) RM0453 32.3 RTC functional description 32.3.1 RTC block diagram Figure 274. RTC block diagram rtc_tamp_evt rtc_its Time stamp detection RTC_TS Time stamp registers RTC_TSTR RTC_TSDR RTC_TSSR RTC_REFIN ck_spre RTC_PRER RTC_CALR RTC_PRER (default 1 Hz) rtc_ker_ck Asynchronous Smooth Synchronous rtc_calovf prescaler...
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Page 991: Table 207. Rtc Input/Output Pins
RM0453 Real-time clock (RTC) 32.3.2 RTC pins and internal signals Table 207. RTC input/output pins Pin name Signal type Description RTC_TS Input RTC timestamp input RTC_REFIN Input RTC 50 or 60 Hz reference clock input RTC_OUT1 Output RTC output 1 RTC_OUT2 Output RTC output 2... -
Page 992: Table 209. Rtc Interconnection
Real-time clock (RTC) RM0453 Table 209. RTC interconnection Signal name Source/destination rtc_its From power controller (PWR): main power loss/switch to V detection output rtc_tamp_evt From TAMP peripheral: tamp_evt rtc_calovf To TAMP peripheral: tamp_itamp5 The triggers outputs can be used as triggers for other peripherals. 32.3.3 GPIOs controlled by the RTC and TAMP The GPIOs included in the battery backup domain (V... - Page 993 RM0453 Real-time clock (RTC) Table 210. PC13 configuration (continued) PC13 Pin function 01 or 10 or Don’t Don’t Don’t Don’t No pull care care care care 01 or 10 or TAMPALRM output 01 or Open-Drain 10 or Internal Don’t Don’t Don’t Don’t pull-up...
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Page 994: Table 211. Rtc_Out Mapping
Real-time clock (RTC) RM0453 Table 210. PC13 configuration (continued) PC13 Pin function Don’t care Wake-up pin or Standard Don’t Don’t GPIO care care Don’t Don’t care care 1. OD: open drain; PP: push-pull. 2. In this configuration the GPIO must be configured in input. In addition, it is possible to output RTC_OUT2 on PA4 pin thanks to OUT2EN bit. - Page 995 RM0453 Real-time clock (RTC) BCD mode (BIN=00) A programmable prescaler stage generates a 1 Hz clock which is used to update the calendar. To minimize power consumption, the prescaler is split into 2 programmable prescalers (see Figure 274: RTC block diagram): •...
- Page 996 Real-time clock (RTC) RM0453 used to define when the calendar is incremented by 1 second, using the SSR least significant bits. 32.3.5 Real-time clock and calendar The RTC calendar time and date registers are accessed through shadow registers which are synchronized with PCLK (APB clock). They can also be accessed directly in order to avoid waiting for the synchronization duration.
- Page 997 RM0453 Real-time clock (RTC) When the binary mode is used, the subsecond field can be programmed in the alarm binary register RTC_ALRMABINR. The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register. Caution: If the seconds field is selected (MSK1 bit reset in RTC_ALRMAR), the synchronous prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct behavior.
- Page 998 Real-time clock (RTC) RM0453 32.3.9 RTC initialization and configuration RTC Binary, BCD or Mixed mode By default the RTC is in BCD mode (BIN = 00 in the RTC_ICSR register): the RTC_SSR register contains the sub-second field SS[15:0], clocked by ck_apre, allowing the generation of a 1 Hz clock to update the calendar registers in BCD format (RTC_TR and RTC_DR).
- Page 999 RM0453 Real-time clock (RTC) If LPCAL=0: INITF is set around 2 RTCCLK cycles after INIT bit is set. If LPCAL=1: INITF is set up to 2 ck_apre cycle after INIT bit is set. To generate a 1 Hz clock for the calendar counter, program both the prescaler factors in RTC_PRER register, plus BIN and BCDU in the RTC_ICSR register.
- Page 1000 Real-time clock (RTC) RM0453 Note: Each change of the RTC_CR register is taken into account after around 2 RTCCLK clock cycles due to clock synchronization. Programming the wake-up timer The following sequence is required to configure or change the wake-up timer auto-reload value (WUT[15:0] in RTC_WUTR): Clear WUTE in RTC_CR to disable the wake-up timer.
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