STMicroelectronics SPC572L series Reference Manual page 620

Embedded Flash Memory (MP55)
Field
Reserved (Read/Write).
2-21
Writes have no effect. For compatibility purposes, any writes should be '0'.
Next Array Integrity Break Point (Read/Clear)
If AIBPE is set, NAIBP is set once a single bit correction (if enabled) or double bit detection is
noted during the Array Integrity test. NAIBP is not writable to '1' but may be cleared to '0'.
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Clearing NAIBP to '0' enables the Array Integrity operation to be re-started after a breakpoint
is encountered. If the Array Integrity operation completes without encountering another
NAIBP
correction or detection, AID is set with NAIBP remaining '0'.
0 Array Integrity is not currently at a break point.
1 Array Integrity is at a break point.
Array Integrity Break Point Enable. (Read/Write)
To enable breakpoints during an Array Integrity test, AIBPE may be set. When breakpoints
are enabled, if the run has been started with MCR[ERR] (and MCR[SBC] when
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UT0[SBCE]=1) flag cleared, on the eventual occurrence of a breakpoint condition, MCR flags
and ADR value may be updated. See NAIBP description for more information about Array
AIBPE
Integrity breakpoints.
0 Array Integrity breakpoints are not enabled.
1 Array Integrity breakpoints are enabled during Array Integrity Checks.
24 Reserved
Array Integrity Suspend (Read/Write).
AISUS toggles Suspend of an Array Integrity - Margin Read Operation.
AISUS can be written to '1' only when AID is low
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AISUS can be written to '0' only when AID is high.
AISUS
Attempting to Write AISUS and AIE on the same clock cycle results in only AIE being written.
0 Array Integrity sequence not suspended.
1 Array Integrity sequence is suspended.
Margin Read Enable (Read/Write)
MRE enables margin reads to be done.
MRE combined with MRV enables User Margin mode reads to be done.
Margin reads run on a block-by-block basis in linear address sequence selected by SEL0,
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SEL1 and SEL2.
MRE
This bit is not accessible when MCR[DONE] or UT0[AID] are low or if AISUS or NAIBP are
high: reading returns indeterminate data while writing has no effect.
0 Margin Read is not enabled.
1 Margin Read is enabled.
Margin Read Value (Read/Write)
If MRE is high, MRV selects the margin level that is being checked. Margin can be checked to
an erased level (MRV=1) or to a programmed level (MRV=0).
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This bit is not accessible whenever MCR[DONE] or UT0[AID] are low or if AISUS or NAIBP
MRV
are high: reading returns indeterminate data while writing has no effect.
0 Zero's (programmed) margin reads are requested (if MRE=1).
1 One's (erased) margin reads are requested (if MRE=1).
Reserved (Read/Write).
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Write this bit has no effect. It's suggested for compatibility to Write at 0.
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Table 312. UT0 field descriptions(Continued)
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Description
RM0400