Exception Syndrome Register (Esr) - STMicroelectronics SPC572L series Reference Manual

RM0400
Interrupt type
none, vector to
System reset [p_rstbase[0:29]]
|| 2'b00
Critical Input 0x00
Machine check 0x10
Machine check
0x10
(NMI)
Data Storage 0x20
Instruction Storage 0x30
External Input 0x40
Alignment 0x50
Program 0x60
Performance
0x70
Monitor
System call 0x80
Debug 0x90
EFPU Data
0xA0
Exception
EFPU Round
0xB0
Exception
TBD 0xC0–0xF0
1. Autovectored Critical Input interrupts use this offset value. Vectored interrupts supply an interrupt vector offset directly.
2. Autovectored External Input interrupts use this offset value. Vectored interrupts supply an interrupt vector offset directly.
12.6.1

Exception Syndrome Register (ESR)

The Exception Syndrome Register (ESR) provides a syndrome to differentiate between
exceptions that can generate the same interrupt type.
Table 94. Exceptions and conditions
Interrupt vector
offset value
Reset
(1)
p_critint_b is asserted and MSR
1. p_mcp_b transitions from negated to asserted
2. ISI or Bus Error on first instruction fetch for an exception handler
3. External bus error
4. Stack limit check failure
Non-Maskable Interrupt
Access control
Access control
(2)
Interrupt Controller interrupt and MSR
1. lmw, stmw not word aligned
2. lwarx or stwcx. not word aligned, lharx or sthcx. not halfword
3. dcbz
Illegal, Privileged, Trap
Performance Monitor Enabled Condition or Event w/PMGC0
Execution of the System Call (se_sc) instruction
Trap, Instruction Address Compare, Data Address Compare, Instruction
Complete, Branch Taken, Return from Interrupt, Interrupt Taken, Debug
Counter, External Debug Event, Unconditional Debug Event,
Performance Monitor Enabled Condition or Event w/PMGC0
See section "Embedded Floating-point Data Exception" in the Power
Architecture core reference manual relative to this core.
See section "Embedded Floating-point Round Exception" in the Power
Architecture core reference manual relative to this core.
Reserved for future processor use
Causing conditions
aligned
DocID027809 Rev 4
Core e200z215An3 description
= 1.
CE
= 1
EE
= 0
UDI
= 1
UDI
267/2058
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