Table 558. Tx Buffer Configuration Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
44.3.5.2.33 Tx FIFO/Queue Status Register (TXFQS)
Address: 0x00C4
0 1 2
R 0 0 0
W
Reset 0 0 0
16 17 18
R 0 0 0
W
Reset 0 0 0

Table 558. Tx Buffer Configuration register field descriptions

Field
0:9 Reserved
Tx FIFO/Queue Full
10
0 Tx FIFO/Queue not full
TFQF
1 Tx FIFO/Queue full
11:15 Tx FIFO/Queue Put Index
TFQPI Tx FIFO/Queue write index pointer, range 0 to 31.
16:18 Reserved
Tx FIFO Get Index
19:23
Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured
TFGI
(TXBC[TFQM] = '1').
24:25 Reserved
Tx FIFO Free Level
26:31
Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero
TFFL
when Tx Queue operation is configured (TXBC[TFQM] = '1')
Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or
a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the
first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx
FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.
3 4 5 6
0 0 0 0
0 0 0 0
19 20 21 22
TFGI
0 0 0 0
Figure 503. Tx FIFO/Queue Status register
DocID027809 Rev 4
7 8 9 10
0 0 0 TFQF
0 0 0 0
23 24 25 26
0 0
0 0 0 0
Description
CAN Subsystem
Access: R
11 12 13 14
TFQPI
0 0 0 0
27 28 29 30
TFFL
0 0 0 0
1039/2058
15
0
31
0
1091