Register Descriptions - STMicroelectronics SPC572L series Reference Manual

System Status and Configuration Module (SSCM)
Offset from
SSCM_BASE
0038h-0048h Reserved
1
See register description for reset value details.
2
No register abort on this location.
53.3.1

Register descriptions

The following registers are available in the SSCM. Those bits that are shaded out are
reserved for future use. To optimize future compatibility, these bits should be masked out
during any read/write operations to avoid conflict with future revisions.
53.3.1.1 System Status Register (STATUS)
The System Status register reflects the current state of the system.
Offset 0000h
0 1
R 0 CER
W w1c
Reset 0 0
1
Reset value depends on the associated option bits in flash memory.
2
Reset value depends on the device status after leaving reset.
Field
Configuration Error. This field indicates that the SSCM has detected a configuration error while loading
DCF clients (with PARITY Enabled). This error may have been detected during the reset sequence.
CER 0 No configuration problem detected by the SSCM
1 1 Device configuration is not correct
If a non-permanent (transient) error is detected, this bit can be cleared by writing a 1. If the error is
permanent, the bit will reappear immediately.
Processor 1 Nexus enable status.
NXEN1
0Processor 1 Nexus disabled.
3
1Processor 1 Nexus enabled
Processor 0 Nexus enable status.
NXEN
0Processor 0 Nexus disabled.
4
1Processor 0 Nexus enabled
1562/2058
Table 884. SSCM memory map(Continued)
Register
2 3 4 5
0 1
0 -2 -2 1
Figure 929. System Status Register (STATUS)
Table 885. STATUS field descriptions
DocID027809 Rev 4
Access
—
6 7 8 9 10
0 0 BMODE
0 0 -2
Description
RM0400
Section/
Reset Value
page
— —
Access: Read/Write
11 12 13 14
VLE 0 0 0
-1 0 0 0
15
0
0