Figure 227. Mc_Cgm Auxiliary Clock 11 Generation Overview - STMicroelectronics SPC572L series Reference Manual

RM0400

Figure 227. MC_CGM Auxiliary Clock 11 Generation Overview

IRCOSC
XOSC
PLL0 PHI
PLL0 PHI1
CGM_AC11_SC Register
24.4.2.1 Auxiliary Clock Dividers
The MC_CGM generates the following derived clocks:
• peripheral clock - controlled by the CGM_AC0_DC0 register
•
Sigma-Delta ADC clock - controlled by the CGM_AC0_DC1 register
• SAR ADC clock - controlled by the CGM_AC0_DC2 register
•
LFAST clock - controlled by the CGM_AC1_DC0 register
• SENT - controlled by the CGM_AC2_DC0 register
•
SYSCLK1 pin clock - controlled by the CGM_AC7_DC0 register
• CCCU clock - controlled by the CGM_AC8_DC0 register
•
FEC reference clock - controlled by the CGM_AC10_DC0 register
• DSPI clock 0 - controlled by the CGM_AC11_DC0 register
•
DSPI clock 1 - controlled by the CGM_AC11_DC1 register
0
1
2
3
CGM_AC11_DC0 Register
CGM_AC11_DC1 Register
DocID027809 Rev 4
Clock Generation Module (MC_CGM)
clock divider
clock divider
(unused)
DSPI clock 0
DSPI clock 1
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