Table 9. Flash Memory And Overlay Ram Map - STMicroelectronics SPC572L series Reference Manual

RM0400
Table 8. Peripheral (PBRIDGE_A) memory map(Continued)
Start address End address
0xFFFF4000 0xFFFF7FFF
0xFFFF8000 0xFFFFBFFF
0xFFFFC000 0xFFFFFFFF
Table 9 contains the detailed flash memory map for the SPC572Lx.
Start address End address
0x00000000 0x003FFFFF
0x00400000 0x00403FFF
0x00404000 0x00407FFF
0x00408000 0x007FFFFF
0x00800000 0x00803FFF
0x00804000 0x00807FFF
0x00808000 0x00FFFFFF
0x01000000 0x0103FFFF
0x01040000 0x0107FFFF
0x01080000 0x010BFFFF
0x010C0000 0x010FFFFF
0x01100000 0x0113FFFF
0x01140000 0x0117FFFF
0x01180000 0x08FFFFFF
0x09000000 0x0903FFFF
0x09040000 0x0907FFFF
0x09080000 0x090BFFFF
Allocated Used
size size
16 KB —
16 KB —
16 KB —

Table 9. Flash memory and overlay RAM map

Allocated
size
Reserved – no overlay
—
UTEST NVM Block – no overlay
16 KB UTEST NVM Block Space 16 KB
16 KB BAF (block0)
—
Data Flash– no overlay
16 KB EEPROM block0
16 KB EEPROM block1
—
Large flash memory blocks – no overlay
256 KB 256 KB Flash block0
256 KB 256 KB Flash block1
256 KB 256 KB Flash block2
256 KB 256 KB Flash block3
256 KB 256 KB Flash block4
256 KB 256 KB Flash block5
—
Large flash blocks – overlay enabled mapping
256 KB 256 KB Flash block0
256 KB 256 KB Flash block1
256 KB 256 KB Flash block2
DocID027809 Rev 4
PBRIDGE
Access
Control
Register
Password and Device Security Module
PCTL2
(PASS)
System Status and Configuration
PCTL1
Module (SSCM)
PCTL0 Boot Assist ROM (BAR)
Complete flash memory
block structure
Reserved
Reserved
Reserved
Reserved
Memory map
Description
RWW Block
partition size
0 8 KB
0 8 KB
1 16 KB
1 16 KB
0 256 KB
0 256 KB
0 256 KB
0 256 KB
0 256 KB
0 256 KB
0 256 KB
0 256 KB
0 256 KB
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