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Password and Device Security Module (PASS)
Offset 0x0100 LOCK0_PG0
0x0110 LOCK0_PG1
0x0120 LOCK0_PG2
0x0130 LOCK0_PG3
0
1
R
X
W
(1)
X
2
Reset
x
1
16
17
R
W
2
2
Reset
x
x
1. This bit is not implemented and its value has no impact on the system.
2. If no DCF records have been written to change the lock state, the bit will reset to '1'.
LOCK0_PGn register functions are as shown in
Field
0
UTEST NVM Lock. This bit is used to lock the UTEST NVM block from programs (erase protection
not needed since UTEST NVM is OTP and not erasable).
TSLOCK
1
This bit is reserved and has no impact on the system.
2–15
Low Block Lock. A value of 1 in a bit of the lock register signifies that the corresponding block is
locked for program and erase.
LOWLOCK
16–31
Mid Block Lock. A value of 1 in a bit of the lock register signifies that the corresponding block is
locked for program and erase.
MIDLOCK
Note:
Lock registers can only be accessed with 32-bit operations.
The initial value of the lock bits is set via DCF records stored in UTEST Flash block and
copied over during reset. The default value before any DCF record is written is '1',
indicating that a block is locked.
During the Customer Delivery life cycle, the user must program a valid password or a DCF
record that writes to this register to unprotect the UTEST for each password group in order
to prevent permanent and irreversible locking of Flash blocks.
Warning:
2000/2058
2
3
4
5
2
2
2
2
x
x
x
x
18
19
20
21
2
2
2
2
x
x
x
x
Figure 1202. LOCK0_PGn register
Table 1132. LOCK0_PGn register field descriptions
Failure to program valid passwords or DCF records for all
password groups before the life cycle matures to OEM
Production renders the part unusable.
6
7
8
9
LOWLOCK
2
2
2
x
x
x
x
22
23
24
25
MIDLOCK
2
2
2
x
x
x
x
Table
Description
DocID027809 Rev 4
Read/Write & DCF Record
10
11
12
2
2
2
2
x
x
x
26
27
28
2
2
2
2
x
x
x
1132.
RM0400
Access: Software
Write
13
14
15
2
2
2
x
x
x
29
30
31
2
2
(2)
x
x
x
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