Figure 550. Read Answer Transfer (Lfast Frame Encapsulation Is Not Shown) - STMicroelectronics SPC572L series Reference Manual

Serial Interprocessor Interface (SIPI)

Figure 550. Read answer transfer (LFAST frame encapsulation is not shown)

MSB
Header
16 bits
=> 16 bit data allocation
=> 8 bit data allocation
Note: For an 8-bit transfer, address bits [31:2] are used as address and bits [1:0] are used as byte
enables.
–
For a 16-bit transfer, address bits [31:1] are used as address and bit [0] is used as half word
enable.
–
1102/2058
Bits[1:0]:
– 00 - byte 3 enabled (MSB)
– 01 - byte 2 enabled
– 10 - byte 1 enabled
– 11 - byte 0 enabled (LSB)
Bit[0]:
– 0 - half-word 1 enabled (MSB)
– 1- half-word 0 enabled (LSB)
DocID027809 Rev 4
Data
32 bits
64 bits
SIPI Frame
Figure 551. Data allocation
MSB
Copy of data
16 bits
MSB
Copy Copy
of of
8 bits
8 bits
Bit Stream Direction
LSB
CRC16
16 bits
data
16 bits
LSB
Copy
data
of
8 bits 8 bits
RM0400
LSB