STMicroelectronics SPC572L series Reference Manual page 165

RM0400
Field
DSPI Configuration
Selects among the different configurations of the DSPI.
2–3
00 SPI
DCONF
01 DSI
10 CSI
11 Reserved
Freeze
Enables the DSPI transfers to be stopped on the next frame boundary when the device enters
4
Debug mode.
FRZ
0 Do not halt serial transfers in debug mode.
1 Halt serial transfers in debug mode.
Modified Timing Format Enable
5
Enables a modified transfer format to be used.
MTFE 0 Modified SPI transfer format disabled.
1 Modified SPI transfer format enabled.
Peripheral Chip Select Strobe Enable
6
Enables the PCS[5]/ PCSS to operate as a PCS Strobe output signal.
PCSSE 0 PCS[5]/ is used as the Peripheral Chip Select[5] signal.
1 PCS[5]/PCSS is used as an active-low PCS Strobe signal.
Receive FIFO Overflow Overwrite Enable
In the RX FIFO overflow condition, configures the DSPI to ignore the incoming serial data or
7
overwrite existing data. If the RX FIFO is full and new data is received, the data from the transfer,
generating the overflow, is ignored or shifted into the shift register.
ROOE
0 Incoming data is ignored.
1 Incoming data is shifted into the shift register.
Peripheral Chip Select x Inactive State
Determines the inactive state of PCSx when DSPI is in Master Mode. This field has no effect
8–15
when DSPI is in Slave Mode. The Slave Select input to DSPI in slave mode is always Active Low.
PCSIS[7:0]
0 The inactive state of PCSx is low.
1 The inactive state of PCSx is high.
16
This read-only bitfield is reserved and always has the value zero.
Reserved
Module Disable
Allows the clock to be stopped to the non-memory-mapped logic in the DSPI effectively putting
the DSPI in a software controlled power-saving state. The default reset value of the MDIS bit is 1.
17
When DSPI is used in Slave Mode, it is recommended to leave this bit set to '0', since a slave
MDIS
doesn't have control over master transactions.
0 Enable DSPI clocks.
1 Allow external logic to disable DSPI clocks.
Disable Transmit FIFO
When the TX FIFO is disabled, the transmit part of the DSPI (both TXFIFO and CMD FIFO)
18
operates as a simplified double-buffered SPI. This bit can only be written when the MDIS bit is
cleared.
DIS_TXF
0 Tx FIFO is enabled.
1 Tx FIFO is disabled.
Table 47. DSPIx_MCR field descriptions(Continued)
DocID027809 Rev 4
Description
Device configuration
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