STMicroelectronics SPC572L series Reference Manual page 231

RM0400
2. POWERUP state is maintained until supply cross the power-on reset threshold: V
high voltage supply.
3. Before software configuration
4. ESR0 configuration moves from strong pull-down to weak pull-up on completion of internal reset sequence
(PHASE3[FUNC]).
5. JTAG interface implements built-in pull-up/pull-down configuration to ensure noise immunity. Worst case is boundary scan
activation, requiring JCOMP to pulse high and following events to occur during JCOMP pulse high:
- 23 TCK events corresponding to12 clock cycles.
- 3 TMS events synchronous with TCK: sequence 0,1,1,0,0,0,0,0,0,0,0,1
- 2 TDI events synchronous with TCK: sequence x,x,x,x,x,0,0,0,1,0,0,x
TCK, TMS, TDI are implementing hysteresis requiring minimum variation
Digital reset is asserted, ensuring that all module registers are reset to power-on value.
9.6.1.2 POWERUP exit
The device exits POWERUP when VDD_LV and VDD_HV are above the internal LVD
thresholds.
9.6.1.2.1 VDD_LV conditions and LVD trimming/enabling sequence
During POWERUP, the enabled LVDs are:
•
LVD098_C
VDD_LV exits POWERUP when:
•
LVD098_C upper threshold is crossed
1. Once the POWERUP exit conditions (low and high voltage) have been verified, the
internal power-on signal is released to all analog modules.
2. The internal RC oscillator module (IRCOSC) starts initialization and provides clock to
the system after t
clock cycles.
LVD096_C, and LVD112_C share the same reference. LVD112_C – LVD096_C >
90 mV ± 5%. This difference provides margin with respect to maximum internal
resistive drop (40 mV at I
3. The device proceeds through the RGM reset sequence: PHASE0–PHASE1–PHASE2–
PHASE3.
4. Voltage detector (LVD) modules are trimmed at the beginning of PHASE3.
–
–
–
–
5. The configurable LVD modules can optionally be unmasked at the end of PHASE3.
Mask information is read as DCF record from the flash UTEST option bits.
When LVD108_C is masked by the application using the flash user option bits, the device
should rely on PORST signal to detect a voltage failure during power-up: PORST must be
released high before proceeding with the power-up sequence, which may increase reset
sequence completion time.
RCSTARTUP
max
Trim values for LVDs are stored as internal DCF records.
The SSCM uses the flash low-voltage (low-speed) read feature to access the DCF
records and apply the trim values to each LVD module.
After analog delay (t
LVDTRIM
have been trimmed and supply is above threshold
the SSCM proceeds with the reset sequence, eventually accessesing the flash at
full speed to read the option bits required to complete device configuration.
DocID027809 Rev 4
. The PMC digital interface reset is released after two RC
) and 50 mV hysteresis addressing external supply drop.
) has elapsed, the PMC acknowledges that all LVDs
Power management
for LV supply, V
PORUP_LV PORUP_HV
for
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