Table 226. Cmu_Csr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
0:7 Reserved
Start frequency measure. The software can only set this bit to start a clock frequency measure. It
8 is reset by hardware when the measure is ready in the CMU_FDR.
SFM 0 Frequency measurement is completed or not yet started
1 Frequency measurement is not completed
9:21 Reserved
Frequency measure clock selection bit. CKSEL1 selects the clock to be measured by the
frequency meter. This only effects CMU instances that utilizes clock metering.
22:23
00 CLKMT0_RMN is selected
CKSEL1 01 Reserved
10 Reserved
11 CLKMT0_RMN is selected
24:28 Reserved
CLKMT0_RMN division factor. These bits specify the CLKMT0_RMN division factor. The output
clock frequency is f
reference clock to compare with CLKMN0_RMT for crystal clock monitor feature.The clock
29:30 division coding is as follows:
RCDIV 00 CLKMT0_RMN divided by 1 (No division)
01 CLKMT0_RMN divided by 2
10 CLKMT0_RMN divided by 4
11 CLKMT0_RMN divided by 8
CLKMN1 monitor enable
31
0 CLKMN1 monitor is disabled
CME
1 CLKMN1 monitor is enabled
23.4.1.2 CMU Frequency Display Register (CMU_FDR)
The FDR is used to determine the measured frequency being monitored by the CMU.
Address: Base + 0004h
0 1
R 0 0
W
Reset 0 0
16 17
R
W
Reset 0 0

Table 226. CMU_CSR field descriptions

CLKMT0_RMN
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
Figure 175. CMU Frequency Display Register (CMU_FDR)
Description
divided by the factor 2
6 7 8
0 0 0 0
0 0 0 0
22 23 24 25
FD[15:0]
0 0 0 0
DocID027809 Rev 4
Clock Monitor Unit (CMU)
RCDIV
. This output clock is used as
Access: User read-only
9 10 11 12
0 0
0 0 0
26 27 28
0 0 0
13 14 15
FD[19:16]
0 0 0
29 30 31
0 0 0
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