Figure 840. Uart — Dma Tx Fsm (Concept Scheme) - STMicroelectronics SPC572L series Reference Manual

LINFlexD
True
50.3.5.8 UART — RX mode
In UART RX mode, the DMA interface requires a DMA RX channel. A single TCD can
control the reception of an entire Rx buffer. The memory map associated with the TCD chain
(RAM area and LINFlexD registers) is given in
Buffer (n)
(2 halfwords FIFO mode)
Buffer (n+1)
1452/2058
Figure 840. UART — DMA Tx FSM (concept scheme)
UART Tx buffer (FIFO mode)
Enables DMA Tx channel request
DMA Tx tranfer (Req/Ack) from RAM
False
Figure 841. UART — RX memory map
LINFlexD regs
DMA transfer (8/16 data format)
BDRM
(4 bytes FIFO mode)
BDRL + DRM
BDRM
(8 bytes)
BDRL
(4 bytes FIFO mode)
BDRL + DRM
BDRM
(8 bytes)
(2 halfwords FIFO mode)
1 DMA RX channel/filter (TCD single and/or linked chain)
SetTXEN
(DMAERQH.DMAERQL)
! TFF & DMA_TEN ?
area to UART Tx FIFO
False
DMA Tx
(major loop) done ?
False
DMA Tx
(minor loop) done?
True
! TFF ?
Table
BDRL + DRM
BDRM (M halfwords)
BDRL + DRM
BDRM (M halfwords)
DocID027809 Rev 4
False
True
False
824.
RAM area
BDRM (M bytes)
(8 bytes)
BDRM (M bytes)
(8 bytes)
RM0400
TCD(n)
TCD(n +1)