Table 649. Differences Between Tsb And Itsb Modes - STMicroelectronics SPC572L series Reference Manual

Deserial Serial Peripheral Interface (DSPI)
Mode attribute
Priority available to frames from SPI. Back to
Frame priority
back SPI frames are sent out.
Selection bit inserted for DSI frames only.
Frame selection bit Selection bit for SPI frames is inserted by
software.
Frame Occasionally triggered transmission (that is
transmission trigger is received via hardware trigger input).
Gap between frames is configurable. Time
Frame gap between frames is t
from 1 to 64 baud rate clock cycles.
In TSB and ITSB mode, separate frame completion interrupts are available to indicate frame
transmission completion from SPI and DSI. MSC dual receiver support with PCS switchover
is also supported in ITSB mode. See
PCS Switchover
The ITSB mode is suitable to implement the Downstream Channel for the MSC Bus
because of the ITSB mode features listed in the table above.
46.5.10.1 Configuring DSPI for ITSB mode
The following steps give the recommended way to initialize the DSPI for the ITSB mode of
operation:
•
The DSPI should be put in HALT mode (by asserting the MCR[HALT] bit) before
programming the registers.
•
Set the DSICR0[TSBC] and DSICR0[ITSB] bits. The DSICR0[CID] bit should be
cleared. DSICR0[DCONT] should not be used in ITSB mode. If DSICR0[ITSB] bit is set
without setting DSICR0[TSBC], then the DSPI operates in the Normal Mode depending
on MCR[DCONF] bit.
•
Enable frame completion interrupts for either any frame completion (TCF) or separate
frame completion (DSITCF and SPITCF) as required by application.
•
When remainder configuration of DSPI is complete, clear the MCR[HALT] bit to allow
DSPI to start operations.
Once configured and DSPI is brought out of HALT, the ITSB mode shall start sequencing the
frames from either DSI or SPI as per the rules mentioned in
TSB (ITSB)
1208/2058

Table 649. Differences between TSB and ITSB modes

TSB mode
which is configurable
DT
for more details.
Mode.
DocID027809 Rev 4
No priority. Messages are interleaved such
that there are no back-to-back SPI frames
Selection bit for both DSI and SPI frames
inserted automatically. Encoding of selection
bit same as TSB mode (0 = DSI; 1 = SPI).
Periodically triggered transmission (that is
frames are transmitted continuously on every
trigger).
Gap between frames is inserted automatically
as the whole operation is based on a periodic
trigger. If a frame has less than 64-bits to be
transmitted, dead or passive time is
automatically inserted by waiting for the next
trigger pulse. Time t
mode as it can be made part of the trigger
period (as passive time).
Section 46.5.9.1: MSC Dual Receiver Support with
ITSB mode
is not used in this
DT
Section 46.5.10: Interleaved
RM0400